[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2023-04-20 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #7 from CVS Commits --- The master branch has been updated by Jeff Law : https://gcc.gnu.org/g:07e2576d6f344acab338deeb051845c90c1cf6a3 commit r14-116-g07e2576d6f344acab338deeb051845c90c1cf6a3 Author: Raphael Zinsly Date: Thu Ap

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2023-04-20 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2022-12-28 Thread andrew at sifive dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2022-12-28 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #2 from Jeffrey A. Law --- It can certainly get "unduly weird". Basically such instructions get put at the end of the ready queue as soon as its input dependencies are satisfied. If there's only a few such instructions, then the re

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2022-12-28 Thread andrew at sifive dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #3 from Andrew Waterman --- Yikes. Thanks for the explanation, Jeff. (cc Kito Cheng: at some point, we should revisit the pipeline modeling of Zb* instructions for sifive-7. The short version is that all Zb* instructions can execu

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2022-12-28 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #4 from Jeffrey A. Law --- Yea, thinking about our uarch, we're going to need finer control as well. There's a subset that ought to execute in any ALU, but there's another subset that are bound to a specific ALU and are potentially

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2023-02-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #5 from Jeffrey A. Law --- So a datapoint in this effort. For the Veyron V1, all the bitmanip instructions except clmul and cpop are single cycle and can be handled by any of the 4 standard ALUs. clmul, cpop are 4c and use the shar

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

2023-02-21 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #6 from Andrew Pinski --- (In reply to Jeffrey A. Law from comment #5) > So a datapoint in this effort. > > For the Veyron V1, all the bitmanip instructions except clmul and cpop are > single cycle and can be handled by any of the 4