[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2024-01-22 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 --- Comment #9 from GCC Commits --- The trunk branch has been updated by Lehua Ding : https://gcc.gnu.org/g:f625c017e60b6e05675b7d6280f2c7677ce691c3 commit r14-8333-gf625c017e60b6e05675b7d6280f2c7677ce691c3 Author: Juzhe-Zhong Date: Mon

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-27 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 Andrew Pinski changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-17 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 --- Comment #7 from CVS Commits --- The master branch has been updated by Kito Cheng : https://gcc.gnu.org/g:02880e7803b19c357718abd2f0d567b4a761f318 commit r13-6733-g02880e7803b19c357718abd2f0d567b4a761f318 Author: Ju-Zhe Zhong Date: Mon

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-14 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 JuzheZhong changed: What|Removed |Added CC||juzhe.zhong at rivai dot ai --- Comment

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-14 Thread ubizjak at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 --- Comment #5 from Uroš Bizjak --- (In reply to Uroš Bizjak from comment #2) > (In reply to Andrew Pinski from comment #1) > > > The issue is register_operand accepts subreg but then REGNO is checked on > > it. > > That is obviously wrong.

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 --- Comment #4 from Jeffrey A. Law --- Also note there's an unsafe REGNO in peephole.md as well. Slightly different in form, but still unprotected and thus for well crafted inputs could probably cause an ICE or incorrect codegen (in a

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-13 Thread jakub at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 Jakub Jelinek changed: What|Removed |Added CC||jakub at gcc dot gnu.org,

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-13 Thread ubizjak at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 --- Comment #2 from Uroš Bizjak --- (In reply to Andrew Pinski from comment #1) > The issue is register_operand accepts subreg but then REGNO is checked on it. > That is obviously wrong. It should be "REG_P (operands[1]) && REGNO >

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-13 Thread rguenth at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 Richard Biener changed: What|Removed |Added Priority|P3 |P1

[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

2023-03-10 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092 Andrew Pinski changed: What|Removed |Added Last reconfirmed||2023-03-10 Target Milestone|---