https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109436
Bug ID: 109436
Summary: AArch64: suboptimal codegen in 128 bit constant stores
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sinan.lin at linux dot alibaba.com
Target Milestone: ---
When splitting a 128-bit constant, there may be cases where the part that is
cut out is a constant 0. And we could use a zero register to avoid the "mov
reg, 0" instruction.
e.g.
```
__int128 Data;
void init() {
Data = 0xfffff;
}
```
gcc
```
init:
adrp x0, .LANCHOR0
add x0, x0, :lo12:.LANCHOR0
mov x2, 1048575
mov x3, 0
stp x2, x3, [x0]
ret
```
clang
```
init:
mov w8, #1048575
adrp x9, Data
add x9, x9, :lo12:Data
stp x8, xzr, [x9]
ret
```
