https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110762
Bug ID: 110762
Summary: inappropriate use of SSE (or AVX) insns for v2sf mode
operations
Product: gcc
Version: 13.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jbeulich at suse dot com
Target Milestone: ---
Perhaps related to work done for bug 95046, this code
typedef float __attribute__((vector_size(8))) v2sf_t;
typedef float __attribute__((vector_size(16))) v4sf_t;
v2sf_t test(v4sf_t x, v4sf_t y) {
v2sf_t x2, y2;
__builtin_ia32_storelps(&x2, x);
__builtin_ia32_storelps(&y2, y);
return x2 + y2;
}
compiled for a 64-bit target with -O2 translates to a single addps (besides the
ret instruction of course), coming from *mmx_addv2sf3. This cannot be right:
The contents of the upper halves of both registers aren't known at this point,
so the extra care mentioned in 95046 does not look to be applied here.
