[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-14 Thread patrick at rivosinc dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #17 from Patrick O'Neill --- (In reply to Robin Dapp from comment #16) > I'd hope it was not fixed by this but just latent because we chose a > VLS-mode vectorization instead. Hopefully we're better off with the fix > than without

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-14 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #16 from Robin Dapp --- I'd hope it was not fixed by this but just latent because we chose a VLS-mode vectorization instead. Hopefully we're better off with the fix than without :)

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-14 Thread patrick at rivosinc dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 Patrick O'Neill changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-14 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #14 from GCC Commits --- The master branch has been updated by Robin Dapp : https://gcc.gnu.org/g:0a5170b5f596bb5fcedf25d93952b979d02d1f56 commit r14-6555-g0a5170b5f596bb5fcedf25d93952b979d02d1f56 Author: Robin Dapp Date: Sun

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-01 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #13 from Robin Dapp --- Mostly an issue because our expander is definitely not prepared to handle that :) It looks like aarch64's is, though, and ours can/should be changed then. aarch64 doesn't need to implement a qi/bi extract

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-01 Thread rguenther at suse dot de via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #12 from rguenther at suse dot de --- On Fri, 1 Dec 2023, rdapp at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 > > --- Comment #11 from Robin Dapp --- > When I define a vec_extract...bi pattern we

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-01 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #11 from Robin Dapp --- When I define a vec_extract...bi pattern we don't enter the if (vec_extract) in expmed because e.g. bitsize = {1, 0} bitnum = {3, 4} and GET_MODE_BITSIZE (innermode) = {1, 0} with innermode = BImode. This

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-01 Thread rguenth at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 Richard Biener changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-01 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #9 from Robin Dapp --- Ok, it's not the fold_extract_last expander. It just appeared that way here because I disabled some other things. What we want to do is extract the last element from a vector. This works as long as we have

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-12-01 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #8 from Robin Dapp --- Thanks for the testcase. It looks pretty similar to the situation why I introduced the bitmask extract in the first place and I don't think that's the root cause. As last time the problem is that the generic

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #7 from JuzheZhong --- Here is the compiler explorer for reference and easily see the issue: https://godbolt.org/z/8v1dsKG3f

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread patrick at rivosinc dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #6 from Patrick O'Neill --- (In reply to JuzheZhong from comment #3) > I see. I didn't reproduce the ICE since I didn't enable gcc_assert_checking. > > Could you tell me how to enable it ? I didn't explicitly enable checking. The

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #5 from JuzheZhong --- Besides, the mask type is: vector([4,4])

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #4 from JuzheZhong --- After reproducing the ICE. I confirm the root cause is because we enable vec_extract for mask: ;; - ;; This extracts a bit (via QImode)

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #3 from JuzheZhong --- I see. I didn't reproduce the ICE since I didn't enable gcc_assert_checking. Could you tell me how to enable it ? I hack the codes as follows: diff --git a/gcc/poly-int.h b/gcc/poly-int.h index

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread patrick at rivosinc dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 Patrick O'Neill changed: What|Removed |Added Attachment #56724|0 |1 is obsolete|

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 JuzheZhong changed: What|Removed |Added CC||juzhe.zhong at rivai dot ai --- Comment

[Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b

2023-11-30 Thread rguenth at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 Richard Biener changed: What|Removed |Added Target Milestone|--- |14.0