[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-15 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 JuzheZhong changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-15 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #11 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:7be87b7d2e330afd14a7cc028f64d88f80e12f40 commit r14-7245-g7be87b7d2e330afd14a7cc028f64d88f80e12f40 Author: Juzhe-Zhong Date: Mon Jan

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-10 Thread pan2.li at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #10 from Li Pan --- (In reply to Robin Dapp from comment #9) > I also noticed this (likely unwanted) vector snippet and wondered where it > is being created. First I thought it's a vec_extract but doesn't look like > it. I'm going

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-10 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #9 from Robin Dapp --- I also noticed this (likely unwanted) vector snippet and wondered where it is being created. First I thought it's a vec_extract but doesn't look like it. I'm going to check why we create this. Pan, the test

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-10 Thread pan2.li at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 Li Pan changed: What|Removed |Added CC||pan2.li at intel dot com --- Comment #8 from

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-10 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #7 from JuzheZhong --- Hi, Robin. I sent a patch switching cost model into generic cost model: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642428.html But I tweak the cost back to default cost. Since current generic

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-09 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #6 from JuzheZhong --- I have tried generic-ooo: https://compiler-explorer.com/z/44dcePczz There are still a few vectorized codes in the last couple lines of assembler: vsetivlizero,4,e32,m1,ta,ma addw

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-09 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #5 from JuzheZhong --- (In reply to Robin Dapp from comment #4) > The other option is to assert that all tune models have at least a vector > cost model rather than NULL... But not falling back to the builtin costs > still makes

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-09 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #4 from Robin Dapp --- The other option is to assert that all tune models have at least a vector cost model rather than NULL... But not falling back to the builtin costs still makes sense.

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-09 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #3 from Robin Dapp --- Yes, sure and I gave a bit of detail why the values chosen there (same as aarch64) make sense to me. Using this generic vector cost model by default without adjusting the latencies is possible. I would be OK

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-09 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #2 from JuzheZhong --- (In reply to Robin Dapp from comment #1) > Hmm, so I tried reproducing this and without a vector cost model we indeed > vectorize. My qemu dynamic instruction count results are not as abysmal as > yours but

[Bug target/113247] RISC-V: Performance bug in SHA256 after enabling RVV vectorization

2024-01-09 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113247 --- Comment #1 from Robin Dapp --- Hmm, so I tried reproducing this and without a vector cost model we indeed vectorize. My qemu dynamic instruction count results are not as abysmal as yours but still bad enough (20-30% increase in dynamic