[Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

2024-02-26 Thread patrick at rivosinc dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

2024-02-23 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 --- Comment #3 from GCC Commits --- The master branch has been updated by Robin Dapp : https://gcc.gnu.org/g:85c12ae8b80902ed46c97f33dbb61533e07f2905 commit r14-9159-g85c12ae8b80902ed46c97f33dbb61533e07f2905 Author: Robin Dapp Date: Thu

[Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

2024-02-22 Thread rdapp at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 --- Comment #2 from Robin Dapp --- This is a target issue. It looks like we try to construct a "superword" sequence when the element size is already == Pmode. Testing a patch.

[Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

2024-02-20 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 --- Comment #1 from Andrew Pinski --- Works fine on aarch64 with SVE: ``` [apinski@xeond2 upstream-full-cross]$ ./install/bin/aarch64-linux-gnu-gcc -O3 t6.c -static -march=armv9-a+sve2 -fno-vect-cost-model [apinski@xeond2 upstream-full-cross]$