[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352 Li Pan changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352 --- Comment #4 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:9941f0295a14659e25260458efd2e46a68ad0342 commit r14-9605-g9941f0295a14659e25260458efd2e46a68ad0342 Author: Pan Li Date: Tue Mar 19

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352 --- Comment #3 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:d3c24e9e55a7cf18df313a8b32b6de4b3ba81013 commit r14-9604-gd3c24e9e55a7cf18df313a8b32b6de4b3ba81013 Author: Pan Li Date: Mon Mar 18

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352 --- Comment #2 from Richard Biener --- *** Bug 114351 has been marked as a duplicate of this bug. ***