https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116197

            Bug ID: 116197
           Summary: [14/15 only] RISC-V: zvkn does not imply "v" extension
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Testcase:
int a, b;
int main() {
  for (; a < 6; a++) {
    b = 8;
    if (a)
      b = 0;
  }
}

Command:
> /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc
>  -O3 -march=rv64imzvkn_d red.c -w -o red.out
> QEMU_CPU=rv64,vlen=64,rvv_ta_all_1s=true,rvv_ma_all_1s=true 
> /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/qemu-riscv64 red.out
zsh: illegal hardware instruction (core dumped) 
QEMU_CPU=rv64,vlen=64,rvv_ta_all_1s=true,rvv_ma_all_1s=true  red.out

v isn't defined in any of the isa strings in the final file:
> /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-readelf
>  -a --wide red.out | grep "rv"
    29: 0000000000010464     0 NOTYPE  LOCAL  DEFAULT   11
$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0
    34: 0000000000010494     0 NOTYPE  LOCAL  DEFAULT   11
$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0
    36: 00000000000103f0     0 NOTYPE  LOCAL  DEFAULT   11
$xrv64i2p1_m2p0_f2p2_d2p2_zicsr2p0_zmmul1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0
    39: 0000000000010496     0 NOTYPE  LOCAL  DEFAULT   11
$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0
  Tag_RISCV_arch:
"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"

Godbolt: https://godbolt.org/z/1PnY6cjs8

>From the zvkn spec:
>The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite 
>extensions Zvkn
>and Zvks-- require a Zve64x base, or application ("V") base Vector Extension.
https://github.com/riscv/riscv-crypto/releases

See also: pr116150

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