[Bug target/20924] [4.0/4.1 regression] inline float divide does not set correct fpu status flags

2005-04-13 Thread cvs-commit at gcc dot gnu dot org
--- Additional Comments From cvs-commit at gcc dot gnu dot org 2005-04-13 15:57 --- Subject: Bug 20924 CVSROOT:/cvs/gcc Module name:gcc Changes by: [EMAIL PROTECTED] 2005-04-13 15:57:38 Modified files: gcc: ChangeLog gcc/config/ia64:

[Bug target/20924] [4.0/4.1 regression] inline float divide does not set correct fpu status flags

2005-04-12 Thread pinskia at gcc dot gnu dot org
--- Additional Comments From pinskia at gcc dot gnu dot org 2005-04-12 17:37 --- Patch here: http://gcc.gnu.org/ml/gcc-patches/2005-04/msg01300.html. -- What|Removed |Added

[Bug target/20924] [4.0/4.1 regression] inline float divide does not set correct fpu status flags

2005-04-11 Thread sje at cup dot hp dot com
--- Additional Comments From sje at cup dot hp dot com 2005-04-11 23:14 --- The problem is that the inline divide instructions are generating frcpa instructions that use the floating point status register (fpsr) 1 when they should be using fpsr 0. I will test a patch overnight and

[Bug target/20924] [4.0/4.1 regression] inline float divide does not set correct fpu status flags

2005-04-10 Thread aj at gcc dot gnu dot org
--- Additional Comments From aj at gcc dot gnu dot org 2005-04-10 07:33 --- This problem shows with running the glibc testsuite. If the inlined functions are used, the functions are not setting the state and this is a violation of ISO C. -- What|Removed

[Bug target/20924] [4.0/4.1 regression] inline float divide does not set correct fpu status flags

2005-04-10 Thread pinskia at gcc dot gnu dot org
-- What|Removed |Added CC||sje at cup dot hp dot com Keywords||wrong-code Target Milestone|---