[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2021-09-27 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2017-09-28 Thread mkuvyrkov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 Maxim Kuvyrkov changed: What|Removed |Added Status|ASSIGNED|UNCONFIRMED Ever confirmed|1

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2014-08-20 Thread mkuvyrkov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 Maxim Kuvyrkov changed: What|Removed |Added Status|NEW |ASSIGNED CC|

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2014-07-29 Thread m.zakirov at samsung dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #9 from Marat Zakirov --- I used following patch diff --git a/gcc/cse.c b/gcc/cse.c index 34f9364..a9e0442 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -2862,6 +2862,9 @@ canon_reg (rtx x, rtx insn) || ! REGNO_QTY_VALID_P (R

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2014-07-29 Thread m.zakirov at samsung dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #8 from Marat Zakirov --- UPDATE Using little fix you may got a much better code... transpose_16x16: .fnstart @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link regi

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2014-07-09 Thread m.zakirov at samsung dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 Marat Zakirov changed: What|Removed |Added CC||joseph at codesourcery dot com,

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2011-06-29 Thread siarhei.siamashka at gmail dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #6 from Siarhei Siamashka 2011-06-29 13:35:13 UTC --- Created attachment 24630 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=24630 test.c Attached a slightly updated testcase, which can demonstrate unnecessary spills to stack e

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2010-10-08 Thread siarhei.siamashka at gmail dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #5 from Siarhei Siamashka 2010-10-08 14:13:08 UTC --- (In reply to comment #3) > On Mon, 4 Oct 2010, siarhei.siamashka at gmail dot com wrote: > > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 > > > > --- Comment #2 from Siarh

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2010-10-05 Thread ramana at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #4 from Ramana Radhakrishnan 2010-10-05 07:16:35 UTC --- (In reply to comment #2) > (In reply to comment #1) > > So the compiler is correct not to be using vld1 for this code. The memory > > format of int32x4_t is defined to be the f

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2010-10-04 Thread joseph at codesourcery dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #3 from joseph at codesourcery dot com 2010-10-04 23:45:57 UTC --- On Mon, 4 Oct 2010, siarhei.siamashka at gmail dot com wrote: > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 > > --- Comment #2 from Siarhei Siamashka > 2010-1

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2010-10-04 Thread siarhei.siamashka at gmail dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 --- Comment #2 from Siarhei Siamashka 2010-10-04 22:59:56 UTC --- (In reply to comment #1) > So the compiler is correct not to be using vld1 for this code. The memory > format of int32x4_t is defined to be the format of a neon register that has

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2010-09-29 Thread rearnsha at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43725 Richard Earnshaw changed: What|Removed |Added Last reconfirmed|2010-05-11 07:35:23 |2010-09-29 7:35:23 date|

[Bug target/43725] Poor instructions selection, scheduling and registers allocation for ARM NEON intrinsics

2010-05-11 Thread ramana at gcc dot gnu dot org
-- ramana at gcc dot gnu dot org changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever Confirmed|0 |1 Keywo