http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52261
Bug #: 52261
Summary: [avr] Add support for AVR Xmega cores
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: g...@gcc.gnu.org
CC: eric.wedding...@atmel.com
Target: avr
Xmega core are special with respect to I-flag instruction and writing SPL (low
byte of stack pointer SP):
In old cores, setting I-flag by means of SEI/RETI/OUT has a latency of 1
instruction
In Xmega cores, setting I-flag by means of SEI/RETI/OUT has a latency of 0
instructions.
This, writing to SP by a sequence like
IN tmp_reg, SREG
CLI
OUT SP_H, %B1
OUT SREG, tmp_reg
OUT SP_L, %A1
is no move correct because write of SP with that sequence is no more atomic.
Xmega's OUT SP_L,* inhibits IRQs for 4 instructions so that the following
sequence can be used instead to write to SP:
OUT SP_L, %A1
OUT SP_H, %B1
