[Bug target/53020] __atomic_fetch_or doesn't generate `1 insn` variant

2012-04-17 Thread ubizjak at gmail dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53020 Uros Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED URL|

[Bug target/53020] __atomic_fetch_or doesn't generate `1 insn` variant

2012-04-17 Thread uros at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53020 --- Comment #4 from uros at gcc dot gnu.org 2012-04-17 17:35:30 UTC --- Author: uros Date: Tue Apr 17 17:35:23 2012 New Revision: 186542 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=186542 Log: PR target/53020 * config/i386/sync.m

[Bug target/53020] __atomic_fetch_or doesn't generate `1 insn` variant

2012-04-17 Thread uros at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53020 --- Comment #5 from uros at gcc dot gnu.org 2012-04-17 17:39:12 UTC --- Author: uros Date: Tue Apr 17 17:39:06 2012 New Revision: 186543 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=186543 Log: PR target/53020 * config/i386/sync.m

[Bug target/53020] __atomic_fetch_or doesn't generate `1 insn` variant

2012-04-17 Thread kirill.yukhin at intel dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53020 --- Comment #3 from Yukhin Kirill 2012-04-17 17:00:34 UTC --- (In reply to comment #2) > Uh... > > Index: config/i386/sync.md > === > --- config/i386/sync.md (revision 186501) > +++

[Bug target/53020] __atomic_fetch_or doesn't generate `1 insn` variant

2012-04-17 Thread ubizjak at gmail dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53020 Uros Bizjak changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/53020] __atomic_fetch_or doesn't generate `1 insn` variant

2012-04-17 Thread kirill.yukhin at intel dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53020 --- Comment #1 from Yukhin Kirill 2012-04-17 16:23:26 UTC --- Instead, of single `locked` instruction, it generates:.L2: movl%eax, %ecx orl $1, %ecx lock cmpxchgl %ecx, (%edx) Similar variant for AND operation: