https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
--- Comment #10 from Jiong Wang ---
Finished a further investigation, looks like the simplest fix to genrate
optimized code for case A is to add one more optimization case in
"eliminate_regs_in_insn".
currently we only optimize "eliminate_reg +
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
Richard Biener changed:
What|Removed |Added
Priority|P3 |P1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
--- Comment #9 from Jiong Wang ---
To summary, given the following testcases:
case A.C
===
void bar(int i)
{
char A[10];
g(A);
f(A[i]);
}
case B.c
===
void bar(int i)
{
char A[10];
char B[10];
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
--- Comment #8 from Jiong Wang ---
while above associate virtual_stack_var_rtx with constant offset actually cause
another hidding issue.
I assume after the association, we are generating cleaner insn sequences.
given the following testcase
vo
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
--- Comment #7 from Jiong Wang ---
(In reply to bin.cheng from comment #6)
> Em, is offset valid for [reg+offset] addressing mode? if it is, why don't we
> transform "reg+reg+offset" into "regX <- reg + reg; [regX + offset];"?
that's because for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
bin.cheng changed:
What|Removed |Added
CC||amker.cheng at gmail dot com
--- Comment #6
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
Ramana Radhakrishnan changed:
What|Removed |Added
Status|NEW |ASSIGNED
Target Milestone|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
--- Comment #5 from Jiong Wang ---
The root cause is AArch64's TARGET_LEGITIMIZE_ADDRESS are not doing well when
the input is ((reg + reg) + offset).
looks like currently we have considered reg + non_normal_offset, and trying to
split non_normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62173
--- Comment #4 from Jiong Wang ---
interesting.
r213488 was doing something right, and I guess it exposed some other hidding
issues which need our investigations.
