[Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target

2016-11-07 Thread jakub at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 --- Comment #5 from Jakub Jelinek --- Author: jakub Date: Mon Nov 7 13:07:32 2016 New Revision: 241903 URL: https://gcc.gnu.org/viewcvs?rev=241903&root=gcc&view=rev Log: PR middle-end/71529 * gcc.target/i386/pr71529.C: Moved to

[Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target

2022-03-05 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 --- Comment #6 from CVS Commits --- The master branch has been updated by Roger Sayle : https://gcc.gnu.org/g:8ea4a34bd0b0a46277b5e077c89cbd86dfb09c48 commit r12-7502-g8ea4a34bd0b0a46277b5e077c89cbd86dfb09c48 Author: Roger Sayle Date: Sat Ma

[Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target

2015-09-29 Thread ienkovich at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 --- Comment #3 from Ilya Enkovich --- Author: ienkovich Date: Tue Sep 29 09:32:40 2015 New Revision: 228231 URL: https://gcc.gnu.org/viewcvs?rev=228231&root=gcc&view=rev Log: gcc/ PR target/65105 * config/i386/i386.c: Include db

[Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target

2015-09-29 Thread ienkovich at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 Ilya Enkovich changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target

2015-02-18 Thread jakub at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 Jakub Jelinek changed: What|Removed |Added CC||jakub at gcc dot gnu.org,

[Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target

2015-02-18 Thread enkovich.gnu at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 --- Comment #2 from Ilya Enkovich --- For this test I see 'plus' and 'minus' ops have DI mode until RA and get GPR pairs: (insn 12 35 13 2 (parallel [ (set (reg:DI 0 ax [orig:98 D.1945 ] [98]) (plus:DI (reg:DI 0 ax [o