[Bug target/68088] [6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 @ aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68088 --- Comment #4 from ktkachov at gcc dot gnu.org --- Author: ktkachov Date: Fri Nov 6 12:04:15 2015 New Revision: 229845 URL: https://gcc.gnu.org/viewcvs?rev=229845=gcc=rev Log: [ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside

[Bug target/68088] [6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 @ aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68088 ktkachov at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug target/68088] [6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 @ aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68088 James Greenhalgh changed: What|Removed |Added Status|NEW |ASSIGNED Last

[Bug target/68088] [6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 @ aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68088 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/68088] [6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 @ aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68088 --- Comment #1 from Andrew Pinski --- Note it might also effect arm*-*-* too but only with -mcpu=cortext-a57 .