https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
Uroš Bizjak changed:
What|Removed |Added
Target Milestone|--- |6.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
Uroš Bizjak changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #12 from uros at gcc dot gnu.org ---
Author: uros
Date: Tue Nov 17 09:45:35 2015
New Revision: 230456
URL: https://gcc.gnu.org/viewcvs?rev=230456&root=gcc&view=rev
Log:
PR target/68263
* config/i386/i386.h (BIGGEST_ALI
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #11 from Yulia Koval ---
>HJ, can you please test the patch for IAMCU, also with AVX target?
Tests are ok for IAMCU target
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #10 from Uroš Bizjak ---
Created attachment 36693
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36693&action=edit
Alternative patch
Alternative patch that does a couple of things:
- always defines BIGGEST_ALIGNMENT to 32 for T
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
H.J. Lu changed:
What|Removed |Added
Attachment #36674|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #8 from H.J. Lu ---
After PR 66250 is fixed, we need to adjust all alignments > 4 bytes
to 4 bytes.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
H.J. Lu changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #6 from H.J. Lu ---
(In reply to Yulia Koval from comment #4)
> Why should TARGET_IAMCU support SSE?
It is about using SSE instructions with IAMCU psABI.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #5 from H.J. Lu ---
Created attachment 36674
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36674&action=edit
A patch
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #4 from Yulia Koval ---
Why should TARGET_IAMCU support SSE?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #3 from Uroš Bizjak ---
(In reply to H.J. Lu from comment #2)
> The maximum stack alignment is 4 byte for IA MCU. That is why
> reload generates misaligned load/store.
It looks to me that BIGGEST_ALIGNMENT is defined in a wrong way.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #2 from H.J. Lu ---
The maximum stack alignment is 4 byte for IA MCU. That is why
reload generates misaligned load/store.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68263
--- Comment #1 from Uroš Bizjak ---
(In reply to H.J. Lu from comment #0)
> Misaligned load/store are only handled for AVX, not SSE.
This is because only AVX supports instructions with unaligned memory operands,
and we have to provide a way to
14 matches
Mail list logo