https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68648
Bug ID: 68648
Summary: [5/6][ARM] ICE: fail to generate BIC(immediate)
instruction
Product: gcc
Version: 5.1.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: cctsai57 at gmail dot com
Target Milestone: ---
/* ICE if "arm-linux-gnueabihf-gcc -O1". */
extern void abort (void);
int __attribute__((noinline))
foo() { return 123; }
int __attribute__((noinline))
bar()
{
int c = 1;
c |= 4294967295 ^ (foo() | 4073709551608);
return c;
}
int main()
{
if (bar() != 0x83fd4005) abort();
}
Compiler version: 5.x, 6.0.0
ICE message:
----------
$ arm-linux-gnueabihf-gcc -O1 test.c
test.c: In function 'bar':
test.c:13:1: error: unrecognizable insn:
}
^
(insn 27 26 11 2 (set (reg:SI 0 r0 [orig:121 D.4254 ] [121])
(and:SI (not:SI (const_int 1 [0x1]))
(reg:SI 0 r0 [orig:121 D.4254 ] [121]))) test.c:12 -1
(nil))
test.c:13:1: internal compiler error: in extract_insn, at recog.c:2343
0x8e52e3 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
../../gcc/rtl-error.c:110
0x8e5319 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
../../gcc/rtl-error.c:118
0x8b9e19 extract_insn(rtx_insn*)
../../gcc/recog.c:2343
0x8b9e81 extract_insn_cached(rtx_insn*)
../../gcc/recog.c:2234
0x6f6a19 cleanup_subreg_operands(rtx_insn*)
../../gcc/final.c:3137
0x8b82cc split_insn
../../gcc/recog.c:2957
0x8bc191 split_all_insns()
../../gcc/recog.c:3011
0x8bc252 rest_of_handle_split_after_reload
../../gcc/recog.c:3958
0x8bc252 execute
../../gcc/recog.c:3987
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.
----------
Description:
I think the above (insn 27 ...) should match arm.md:andsi_notsi_si
define_insn pattern but fail because (match_operand 2 ...) does not
accept (const_int 1).
The following patch may fix this problem and generate "bic r0, r0, #0"
successfully.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b380763..0eff5ae 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2786,7 +2786,7 @@
(define_insn "andsi_notsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
- (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
+ (and:SI (not:SI (match_operand:SI 2 "reg_or_int_operand" "rI"))
(match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_32BIT"
"bic%?\\t%0, %1, %2"
