[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411 --- Comment #5 from Jim Wilson --- Author: wilson Date: Tue Mar 19 22:33:34 2019 New Revision: 269813 URL: https://gcc.gnu.org/viewcvs?rev=269813=gcc=rev Log: RISC-V: Fix %lo overflow with BLKmode references. gcc/ PR

[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411 --- Comment #4 from Jim Wilson --- Created attachment 45925 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45925=edit work in progress patches for a fix This implements two ways to fix it, a simple way that just fails for BLKmode, and a

[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411 Jim Wilson changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411 Tao Wang changed: What|Removed |Added CC||wangtao42 at huawei dot com --- Comment #2

[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment #1