[Bug target/90346] gcc generates the "lfence" instruction on CPUs that don't support it

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90346 --- Comment #5 from mikulas at artax dot karlin.mff.cuni.cz --- On non-SSE2 CPUs, it should generate "lock; addl $0,(%esp)" That provides barrier equivalent to "mfence"

[Bug target/90346] gcc generates the "lfence" instruction on CPUs that don't support it

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90346 Martin Liška changed: What|Removed |Added Status|ASSIGNED|NEW Assignee|marxin at gcc dot

[Bug target/90346] gcc generates the "lfence" instruction on CPUs that don't support it

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90346 Martin Liška changed: What|Removed |Added CC||hjl.tools at gmail dot com,

[Bug target/90346] gcc generates the "lfence" instruction on CPUs that don't support it

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90346 Martin Liška changed: What|Removed |Added Status|NEW |ASSIGNED CC|

[Bug target/90346] gcc generates the "lfence" instruction on CPUs that don't support it

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90346 Richard Biener changed: What|Removed |Added Keywords||wrong-code