[gcc r15-647] RISC-V: Implement -m{,no}fence-tso

https://gcc.gnu.org/g:a6114c2a691112f9cf5b072c21685d2e43c76d81 commit r15-647-ga6114c2a691112f9cf5b072c21685d2e43c76d81 Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso`

[gcc r13-8777] [committed] Fix RISC-V missing stack tie

https://gcc.gnu.org/g:162c441c9462d073c53dde87258898795bf28a5c commit r13-8777-g162c441c9462d073c53dde87258898795bf28a5c Author: Jeff Law Date: Thu Mar 21 20:41:59 2024 -0600 [committed] Fix RISC-V missing stack tie As some of you know, Raphael has been working on stack-clash

[gcc r15-646] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 commit r15-646-g3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

https://gcc.gnu.org/g:a5445260bd42d74aabe6c11d6207d113aafe2c8c commit a5445260bd42d74aabe6c11d6207d113aafe2c8c Author: Xiao Zeng Date: Wed May 15 16:23:16 2024 +0800 RISC-V: Fix "Nan-box the result of movbf on soft-bf16" 1 According to unpriv-isa spec:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Modify _Bfloat16 to __bf16

https://gcc.gnu.org/g:af9118f721e8d586049ff4a60ff7bc5507478344 commit af9118f721e8d586049ff4a60ff7bc5507478344 Author: Xiao Zeng Date: Fri May 17 13:48:21 2024 +0800 RISC-V: Modify _Bfloat16 to __bf16 According to the description in:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:d6cb9a0d984a6c9ea0b548178a5cf79629be073b commit d6cb9a0d984a6c9ea0b548178a5cf79629be073b Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores more

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:db2b829f4d45c6f14724148d1f8b2066290b3371 commit db2b829f4d45c6f14724148d1f8b2066290b3371 Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv backend as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:17dfc9744f4995d3161eeba104bd86391005769b commit 17dfc9744f4995d3161eeba104bd86391005769b Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch removes

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup some temporally files [NFC]

https://gcc.gnu.org/g:586e678cd18c8d7a72e5f785094d911a098092ff commit 586e678cd18c8d7a72e5f785094d911a098092ff Author: Pan Li Date: Fri May 17 07:45:19 2024 +0800 RISC-V: Cleanup some temporally files [NFC] Just notice some temporally files under gcc/config/riscv, deleted as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorizable early exit testsuite

https://gcc.gnu.org/g:c1ad575242ff3dee66f2775412b1c65efbc2269b commit c1ad575242ff3dee66f2775412b1c65efbc2269b Author: Pan Li Date: Thu May 16 10:04:10 2024 +0800 RISC-V: Enable vectorizable early exit testsuite After we supported vectorizable early exit in RISC-V, we would like

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vectorizable early exit with vcond_mask_len

https://gcc.gnu.org/g:b1aab03aed7f3d8c9b104b5f596e7e9853b8d5e6 commit b1aab03aed7f3d8c9b104b5f596e7e9853b8d5e6 Author: Pan Li Date: Thu May 16 10:02:40 2024 +0800 RISC-V: Implement vectorizable early exit with vcond_mask_len After we support the loop lens for the vectorizable,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support loop len in vectorizable early exit

https://gcc.gnu.org/g:4ec3a6b6022c1853cfd5866dea0324a4002413b2 commit 4ec3a6b6022c1853cfd5866dea0324a4002413b2 Author: Pan Li Date: Thu May 16 09:58:13 2024 +0800 Vect: Support loop len in vectorizable early exit This patch adds early break auto-vectorization support for target

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int

https://gcc.gnu.org/g:51b69c80a76ba767ed166e93a569a84dae445b23 commit 51b69c80a76ba767ed166e93a569a84dae445b23 Author: Pan Li Date: Wed May 15 10:14:05 2024 +0800 Internal-fn: Support new IFN SAT_ADD for unsigned scalar int This patch would like to add the middle-end presentation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support new IFN SAT_ADD for unsigned vector int

https://gcc.gnu.org/g:674362d73e964815cdb700edd9fedbfc34c24c21 commit 674362d73e964815cdb700edd9fedbfc34c24c21 Author: Pan Li Date: Wed May 15 10:14:06 2024 +0800 Vect: Support new IFN SAT_ADD for unsigned vector int For vectorize, we leverage the existing vect pattern recog to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests

https://gcc.gnu.org/g:faf2f9ed73969d838026027566473bde14db748b commit faf2f9ed73969d838026027566473bde14db748b Author: Christoph Müllner Date: Thu May 16 09:53:47 2024 +0200 RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests The tests cmpmemsi-1.c and cpymemsi-1.c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zvfbfwma extension to the -march= option

https://gcc.gnu.org/g:67195fbc4deac8659d8f65ab922416ac451ae5bb commit 67195fbc4deac8659d8f65ab922416ac451ae5bb Author: Xiao Zeng Date: Wed May 15 10:03:40 2024 +0800 RISC-V: Add Zvfbfwma extension to the -march= option This patch would like to add new sub extension (aka Zvfbfwma)

[gcc r14-10217] AVR: target/115065 - Tweak __clzhi2.

https://gcc.gnu.org/g:3b88dade7ff8a07fd0843ac1281e095cfd94453e commit r14-10217-g3b88dade7ff8a07fd0843ac1281e095cfd94453e Author: Wolfgang Hospital Date: Sat May 18 15:02:51 2024 +0200 AVR: target/115065 - Tweak __clzhi2. The libgcc implementation of __clzhi2 can be tweaked by

[gcc r15-645] AVR: target/115065 - Tweak __clzhi2.

https://gcc.gnu.org/g:988838da722dea09bd81ee9d49800a6f24980372 commit r15-645-g988838da722dea09bd81ee9d49800a6f24980372 Author: Wolfgang Hospital Date: Sat May 18 15:02:51 2024 +0200 AVR: target/115065 - Tweak __clzhi2. The libgcc implementation of __clzhi2 can be tweaked by

gcc-wwwdocs branch master updated. d0ff325b9f7d8e9462cda905c918f110c02c764b

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