[gcc r16-3387] Remove STMT_VINFO_REDUC_VECTYPE_IN

https://gcc.gnu.org/g:0240c52eb6772c3139dfd27fc8fd4ac73c1014b2 commit r16-3387-g0240c52eb6772c3139dfd27fc8fd4ac73c1014b2 Author: Richard Biener Date: Mon Aug 25 14:40:27 2025 +0200 Remove STMT_VINFO_REDUC_VECTYPE_IN This was added when invariants/externals outside of SLP didn't ha

[gcc r16-3386] i386: Fix up recent changes to use GFNI for rotates/shifts [PR121658]

https://gcc.gnu.org/g:d551f88f88b821dc80de9d39c5b275a3678b3e31 commit r16-3386-gd551f88f88b821dc80de9d39c5b275a3678b3e31 Author: Jakub Jelinek Date: Tue Aug 26 06:43:39 2025 +0200 i386: Fix up recent changes to use GFNI for rotates/shifts [PR121658] The vgf2p8affineqb_ pattern use

[gcc r15-10261] c++: constrained corresponding using from partial spec [PR121351]

https://gcc.gnu.org/g:ab7ce5ddb774594a4d82dda65bc4bf83a3d673b3 commit r15-10261-gab7ce5ddb774594a4d82dda65bc4bf83a3d673b3 Author: Patrick Palka Date: Tue Aug 19 11:07:14 2025 -0400 c++: constrained corresponding using from partial spec [PR121351] When comparing constraints during

[gcc r16-3384] RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:74f139fa21da39b03f6dae8597959088e81b6130 commit r16-3384-g74f139fa21da39b03f6dae8597959088e81b6130 Author: Pan Li Date: Tue Aug 19 09:32:22 2025 +0800 RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15 Add asm dump che

[gcc r16-3383] RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:ed2f4bff8bbe7645396c39c924c7e6f1e2af56d6 commit r16-3383-ged2f4bff8bbe7645396c39c924c7e6f1e2af56d6 Author: Pan Li Date: Tue Aug 19 09:30:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15 Add asm dump check

[gcc r16-3382] RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost

https://gcc.gnu.org/g:25037a02716ad0da0f4987960b815dec1f014b1e commit r16-3382-g25037a02716ad0da0f4987960b815dec1f014b1e Author: Pan Li Date: Sat Aug 23 12:55:50 2025 +0800 RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-3381] omp-expand: Initialize fd->loop.n2 if needed for the zero iter case [PR121453]

https://gcc.gnu.org/g:948f20cc520e50968f8759b173096358dcbba3de commit r16-3381-g948f20cc520e50968f8759b173096358dcbba3de Author: Jakub Jelinek Date: Tue Aug 26 00:28:10 2025 +0200 omp-expand: Initialize fd->loop.n2 if needed for the zero iter case [PR121453] When expand_omp_for_i

[gcc r16-3380] Add a test for PR tree-optimization/121656

https://gcc.gnu.org/g:1b6b27536311afefaebf57ff77ed20a8bb41eadd commit r16-3380-g1b6b27536311afefaebf57ff77ed20a8bb41eadd Author: H.J. Lu Date: Mon Aug 25 08:20:00 2025 -0700 Add a test for PR tree-optimization/121656 PR tree-optimization/121656 * gcc.dg/pr12165

[gcc r16-3379] ctf: avoid overflow for array num elements [PR121411]

https://gcc.gnu.org/g:c77d79785d32b30502c8bcd6aa53b63d715bb124 commit r16-3379-gc77d79785d32b30502c8bcd6aa53b63d715bb124 Author: David Faust Date: Wed Aug 6 09:24:40 2025 -0700 ctf: avoid overflow for array num elements [PR121411] CTF array encoding uses uint32 for number of eleme

[gcc r16-3378] forwprop: Boolify simplify_permutation

https://gcc.gnu.org/g:490948d95194b2ae8056fc838c977c977404b97a commit r16-3378-g490948d95194b2ae8056fc838c977c977404b97a Author: Andrew Pinski Date: Sun Aug 24 14:07:44 2025 -0700 forwprop: Boolify simplify_permutation After the return type of remove_prop_source_from_use was chang

[gcc r16-3377] Forwprop: boolify forward_propagate_into_comparison

https://gcc.gnu.org/g:b74fcd033071ca77754427dec682b5f8d3e93dcd commit r16-3377-gb74fcd033071ca77754427dec682b5f8d3e93dcd Author: Andrew Pinski Date: Sun Aug 24 13:45:00 2025 -0700 Forwprop: boolify forward_propagate_into_comparison After changing the return type of remove_prop_sou

[gcc r16-3376] forwprop: Remove return type of remove_prop_source_from_use

https://gcc.gnu.org/g:dbed17b1ee2e1c119eb21b9a5fefce582675a9e3 commit r16-3376-gdbed17b1ee2e1c119eb21b9a5fefce582675a9e3 Author: Andrew Pinski Date: Sun Aug 24 13:33:21 2025 -0700 forwprop: Remove return type of remove_prop_source_from_use Since r5-4705-ga499aac5dfa5d9, remove_pro

[gcc r16-3375] forwprop: Mark the old switch index for (maybe) dceing

https://gcc.gnu.org/g:22d623dca3a8f3854a789f52c4a01e71c57a8724 commit r16-3375-g22d623dca3a8f3854a789f52c4a01e71c57a8724 Author: Andrew Pinski Date: Sat Aug 23 23:47:22 2025 -0700 forwprop: Mark the old switch index for (maybe) dceing While looking at this code I noticed that we d

[gcc r16-3374] Rewrite bool loads for undefined case [PR121279]

https://gcc.gnu.org/g:7269aa0765415df071778b92bd9ecea82f8ea5b2 commit r16-3374-g7269aa0765415df071778b92bd9ecea82f8ea5b2 Author: Andrew Pinski Date: Fri Aug 15 16:17:35 2025 -0700 Rewrite bool loads for undefined case [PR121279] Just like r16-465-gf2bb7ffe84840d8 but this time

[gcc r16-3373] LIM: Manually put uninit decl into ssa

https://gcc.gnu.org/g:2e1dfaad2ae7f11e1ea16f5f419d82d6cbd50c3d commit r16-3373-g2e1dfaad2ae7f11e1ea16f5f419d82d6cbd50c3d Author: Andrew Pinski Date: Tue Aug 19 14:52:18 2025 -0700 LIM: Manually put uninit decl into ssa When working on PR121279, I noticed that lim would create

[gcc r16-3372] xtensa: Make use of compact insn definition syntax for insns whose have multiple alternatives

https://gcc.gnu.org/g:e2533e488fe664371ef120899118e179c5c9fbe7 commit r16-3372-ge2533e488fe664371ef120899118e179c5c9fbe7 Author: Takayuki 'January June' Suwa Date: Mon Aug 25 06:30:05 2025 +0900 xtensa: Make use of compact insn definition syntax for insns whose have multiple alternatives

[gcc r16-3371] xtensa: Simplify "*masktrue_const_bitcmpl" insn pattern

https://gcc.gnu.org/g:b11ee352ca75fb33c1679d07f706b98fa6bb9ce4 commit r16-3371-gb11ee352ca75fb33c1679d07f706b98fa6bb9ce4 Author: Takayuki 'January June' Suwa Date: Mon Aug 25 06:27:43 2025 +0900 xtensa: Simplify "*masktrue_const_bitcmpl" insn pattern gcc/ChangeLog:

[gcc r16-3370] xtensa: Simplify "zero_extend[hq]isi2" insn patterns

https://gcc.gnu.org/g:ee8f20d61dfaa5cf2af77e49e3ad78ccd4d98b36 commit r16-3370-gee8f20d61dfaa5cf2af77e49e3ad78ccd4d98b36 Author: Takayuki 'January June' Suwa Date: Mon Aug 25 06:26:41 2025 +0900 xtensa: Simplify "zero_extend[hq]isi2" insn patterns gcc/ChangeLog: *

[gcc r16-3369] c++: Implement C++ CWG3048 - Empty destructuring expansion statements

https://gcc.gnu.org/g:05baaa6feb9a8093646113c95f4cb8590ddd6de8 commit r16-3369-g05baaa6feb9a8093646113c95f4cb8590ddd6de8 Author: Jakub Jelinek Date: Mon Aug 25 16:29:17 2025 +0200 c++: Implement C++ CWG3048 - Empty destructuring expansion statements The following patch implements

[gcc r16-3368] c++: Check for *jump_target earlier in cxx_bind_parameters_in_call [PR121601]

https://gcc.gnu.org/g:52c29a6a9dac6caec24b75cae17ecb3558c39504 commit r16-3368-g52c29a6a9dac6caec24b75cae17ecb3558c39504 Author: Jakub Jelinek Date: Mon Aug 25 16:27:35 2025 +0200 c++: Check for *jump_target earlier in cxx_bind_parameters_in_call [PR121601] The following testcase

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Read extension data from riscv-ext*.def for arch-canonicalize

https://gcc.gnu.org/g:0ceaec1e3c20e3987068d48db1c53daa795fa4e8 commit 0ceaec1e3c20e3987068d48db1c53daa795fa4e8 Author: Kito Cheng Date: Thu Jul 31 16:25:52 2025 +0800 RISC-V: Read extension data from riscv-ext*.def for arch-canonicalize Previously, arch-canonicalize used hardcoded

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support -march=unset

https://gcc.gnu.org/g:5ab4a75b6cdd05cc1bb0cdd2df31b23a838a622a commit 5ab4a75b6cdd05cc1bb0cdd2df31b23a838a622a Author: Kito Cheng Date: Mon Jul 28 20:49:39 2025 +0800 RISC-V: Support -march=unset This patch introduces a new `-march=unset` option for RISC-V GCC that allows user

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix scalar code-gen of unsigned SAT_MUL

https://gcc.gnu.org/g:e479452e7692f075bf74d6efb02af0a6e75e509d commit e479452e7692f075bf74d6efb02af0a6e75e509d Author: Pan Li Date: Thu Jul 31 12:32:24 2025 +0800 RISC-V: Fix scalar code-gen of unsigned SAT_MUL The previous code-gen of scalar unsigned SAT_MUL, aka usmul. Lever

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed avg ceil vx combine

https://gcc.gnu.org/g:52b5390ce0f0c1bb6ec5072c639520d13e631c3c commit 52b5390ce0f0c1bb6ec5072c639520d13e631c3c Author: Pan Li Date: Wed Jul 30 14:21:02 2025 +0800 RISC-V: Add testcases for signed avg ceil vx combine The unsigned avg ceil share the vaaddx.vx for the vx combine,

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding H to the canonical order [PR121312]

https://gcc.gnu.org/g:f6a6b35e612300e70f350879f178cee50aa0d154 commit f6a6b35e612300e70f350879f178cee50aa0d154 Author: Kito Cheng Date: Thu Jul 31 11:02:45 2025 +0800 RISC-V: Adding H to the canonical order [PR121312] We added H into canonical order before, but forgot to add it to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove use of structured binding to fix compiler warning

https://gcc.gnu.org/g:30259f61fdd11124e25c47b4b5a3c570c2f312b1 commit 30259f61fdd11124e25c47b4b5a3c570c2f312b1 Author: Christoph Müllner Date: Mon Jul 28 17:31:06 2025 +0200 RISC-V: Remove use of structured binding to fix compiler warning Function riscv_ext_is_subset () uses struc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Generate -mcpu and -mtune options from riscv-cores.def.

https://gcc.gnu.org/g:b5bfad99f80c03b8326acf88500a6d7a6ef2dc90 commit b5bfad99f80c03b8326acf88500a6d7a6ef2dc90 Author: Dongyan Chen Date: Wed Jun 25 21:20:25 2025 +0800 RISC-V: Generate -mcpu and -mtune options from riscv-cores.def. Automatically generate -mcpu and -mtune options

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for mul based unsigned scalar SAT_MUL

https://gcc.gnu.org/g:5e1b6024097bc2377bd924d22e6d5640bfec5634 commit 5e1b6024097bc2377bd924d22e6d5640bfec5634 Author: Pan Li Date: Sat Jul 26 16:38:23 2025 +0800 RISC-V: Add test cases for mul based unsigned scalar SAT_MUL Add run and tree-optimized check for mul based unsigned s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned avg ceil vx combine.

https://gcc.gnu.org/g:d848d8f277cd89048644f88de8f8fe0eb307c3c6 commit d848d8f277cd89048644f88de8f8fe0eb307c3c6 Author: Pan Li Date: Mon Jul 28 20:12:31 2025 +0800 RISC-V: Add testcases for unsigned avg ceil vx combine. The unsigned avg ceil share the vaaddux.vx for the vx combine,

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for vaadd.vx combine polluting VXRM

https://gcc.gnu.org/g:99e0eab97a814b9c914bd8a57af2056e6be2c9bc commit 99e0eab97a814b9c914bd8a57af2056e6be2c9bc Author: Pan Li Date: Fri Jul 25 21:29:29 2025 +0800 RISC-V: Add test case for vaadd.vx combine polluting VXRM Add asm check to make sure vx combine of vaadd.vx will not p

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:db175895c1d7b22f70c2add7c3448e1582905ae2 commit db175895c1d7b22f70c2add7c3448e1582905ae2 Author: Pan Li Date: Fri Jul 25 21:28:24 2025 +0800 RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:573df94c988e262affe475f3d67671064d13b819 commit 573df94c988e262affe475f3d67671064d13b819 Author: Pan Li Date: Fri Jul 25 21:26:27 2025 +0800 RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 0, 1 and 15 Add asm dump check and run t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost

https://gcc.gnu.org/g:6ed73317639ac199903f7c6f18e3709e5ad7fc01 commit 6ed73317639ac199903f7c6f18e3709e5ad7fc01 Author: Pan Li Date: Fri Jul 25 21:22:47 2025 +0800 RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix another vf FP16 combine run test failures

https://gcc.gnu.org/g:d7386b26831de7be78d10ebc0a5997c67b5ca85d commit d7386b26831de7be78d10ebc0a5997c67b5ca85d Author: Pan Li Date: Fri Jul 25 22:11:13 2025 +0800 RISC-V: Fix another vf FP16 combine run test failures Like Robin's fix for vf combine f16.c run tests, there is still

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Prepare dynamic LMUL heuristic for SLP.

https://gcc.gnu.org/g:253df77c89a1a1b4d8cb6b6cdb192a2eb5a10a8c commit 253df77c89a1a1b4d8cb6b6cdb192a2eb5a10a8c Author: Robin Dapp Date: Mon Jul 21 16:00:51 2025 +0200 RISC-V: Prepare dynamic LMUL heuristic for SLP. This patch prepares the dynamic LMUL vector costing to use the com

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: riscv-ext.def: Add allocated group IDs and group bit positions

https://gcc.gnu.org/g:0e620263c69d7a6340a96dc09f0f3cbf369ada87 commit 0e620263c69d7a6340a96dc09f0f3cbf369ada87 Author: Christoph Müllner Date: Tue Jun 10 10:53:54 2025 +0200 RISC-V: riscv-ext.def: Add allocated group IDs and group bit positions The riscv-c-api-doc defines a group

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove user-level interrupts

https://gcc.gnu.org/g:c66e78e4beb5616af42a2ddb93f82d3958710fca commit c66e78e4beb5616af42a2ddb93f82d3958710fca Author: Christoph Müllner Date: Fri Jul 25 10:27:59 2025 +0200 RISC-V: Remove user-level interrupts There was once a RISC-V extension draft ("N"), which introduced us

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for vx combine polluting VXRM

https://gcc.gnu.org/g:68fdfa96c0c53815c743e0deacddf23e8027383e commit 68fdfa96c0c53815c743e0deacddf23e8027383e Author: Pan Li Date: Wed Jul 23 13:02:55 2025 +0800 RISC-V: Add test case for vx combine polluting VXRM Add asm check to make sure vx combine of vaaddu.vx will not pollut

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers

https://gcc.gnu.org/g:a456482e4d743b324933688869cd6c74a318ee02 commit a456482e4d743b324933688869cd6c74a318ee02 Author: Christoph Müllner Date: Thu Jul 24 23:08:40 2025 +0200 RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers The Smrnmi extension introduces th

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr

https://gcc.gnu.org/g:4e0e71d1fe2830b8bd83bd30b76157a34cc01448 commit 4e0e71d1fe2830b8bd83bd30b76157a34cc01448 Author: Pan Li Date: Wed Jul 23 12:08:02 2025 +0800 RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr The vaaddu.vx combine almost comes from avg_floor, it will

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] riscv: testsuite: Fix misalignment check.

https://gcc.gnu.org/g:c8e57bc84bfb4ee7720bcaf93c0bae50f9279957 commit c8e57bc84bfb4ee7720bcaf93c0bae50f9279957 Author: Robin Dapp Date: Wed Jul 2 10:28:57 2025 +0200 riscv: testsuite: Fix misalignment check. This fixes a thinko in the misalignment check. If we want to check for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rework broadcast handling [PR121073].

https://gcc.gnu.org/g:e59fca8a497d2495227794ba1b9c3625bc5a409b commit e59fca8a497d2495227794ba1b9c3625bc5a409b Author: Robin Dapp Date: Thu Jul 17 11:09:43 2025 +0200 RISC-V: Rework broadcast handling [PR121073]. During the last weeks it became clear that our current broadcast

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.

https://gcc.gnu.org/g:3045d930e849f1754384d7636b2df2c63ff9ffc4 commit 3045d930e849f1754384d7636b2df2c63ff9ffc4 Author: Robin Dapp Date: Mon Jul 21 15:32:09 2025 +0200 RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests. This patch fixes the vf_vfmacc-run-1-f16.c test failures on r

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Change bellow in comments to below

https://gcc.gnu.org/g:7f0f69976d4e6722689eec342bdf0d0a639db0f9 commit 7f0f69976d4e6722689eec342bdf0d0a639db0f9 Author: Jakub Jelinek Date: Thu Jul 10 10:16:43 2025 +0200 Change bellow in comments to below While I'm not a native English speaker, I believe all the uses of bellow

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Restrict generic-vector-ooo DFA

https://gcc.gnu.org/g:de873d0f1dabdb207bee82aa7c31dda567657f4c commit de873d0f1dabdb207bee82aa7c31dda567657f4c Author: Jeff Law Date: Tue Jul 22 07:26:57 2025 -0600 [RISC-V] Restrict generic-vector-ooo DFA So while debugging Austin's work to support the spacemit x60 in the BPI we

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md

https://gcc.gnu.org/g:8e2532bb022ec4a6607675a362b06b79a7fd1526 commit 8e2532bb022ec4a6607675a362b06b79a7fd1526 Author: Jeff Law Date: Mon Jul 21 15:58:12 2025 -0600 [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md This is a trivial patch to add a few missing types

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode

https://gcc.gnu.org/g:625dba40555b86e39549bc1d53f92288dd3aafbd commit 625dba40555b86e39549bc1d53f92288dd3aafbd Author: Pan Li Date: Mon Jul 21 09:28:06 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode Add asm dump check and run test for vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI

https://gcc.gnu.org/g:9c72d9243173e9fa7d87a4881b89c85695257067 commit 9c72d9243173e9fa7d87a4881b89c85695257067 Author: Pan Li Date: Mon Jul 21 09:16:17 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI and SI mode Add a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow VLS DImode for sat_op vx DImode pattern

https://gcc.gnu.org/g:85bab69e11735729909607c1ad59db2ff6bf08e3 commit 85bab69e11735729909607c1ad59db2ff6bf08e3 Author: Pan Li Date: Mon Jul 21 09:20:46 2025 +0800 RISC-V: Allow VLS DImode for sat_op vx DImode pattern When try to introduce the vaaddu.vx combine for DImode, we will

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI

https://gcc.gnu.org/g:7300f3c02e93893aa0fd52c330e026069588c366 commit 7300f3c02e93893aa0fd52c330e026069588c366 Author: Pan Li Date: Mon Jul 21 09:13:27 2025 +0800 RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI and SI mode Add

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

https://gcc.gnu.org/g:c3e31ff90222d1a20c3b2fc4c1802938074b1718 commit c3e31ff90222d1a20c3b2fc4c1802938074b1718 Author: panciyan Date: Mon Jul 21 01:41:31 2025 + RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9 This patch adds testcase for form8 and form9, as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC]

https://gcc.gnu.org/g:4e0886f0925141d3579c19dcf248eb5c11de48f1 commit 4e0886f0925141d3579c19dcf248eb5c11de48f1 Author: Pan Li Date: Sat Jul 19 10:49:15 2025 +0800 RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] The previous test case doesn't leverage the right

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode

https://gcc.gnu.org/g:9be4e27d3b17d496d258f55d514775726af19d1e commit 9be4e27d3b17d496d258f55d514775726af19d1e Author: Pan Li Date: Mon Jul 21 09:06:52 2025 +0800 RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode This patch would like to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil

https://gcc.gnu.org/g:4c810e2c7f86bb93c63dc064b076d055b083cd8d commit 4c810e2c7f86bb93c63dc064b076d055b083cd8d Author: Pan Li Date: Sat Jul 19 17:17:11 2025 +0800 RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil According to the semantics of the avg_floor and avg_c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:1ef04f18628bfc467697307c3d1016c624ffe607 commit 1ef04f18628bfc467697307c3d1016c624ffe607 Author: Paul-Antoine Arras Date: Sat Jul 19 08:40:14 2025 -0600 [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100] This pattern enab

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix vsetvl merge rule.

https://gcc.gnu.org/g:568d5f2a7965277fede70a48b65d78ab88108baa commit 568d5f2a7965277fede70a48b65d78ab88108baa Author: Robin Dapp Date: Mon Jul 14 13:53:12 2025 +0200 RISC-V: Fix vsetvl merge rule. In PR120297 we fuse vsetvl e8,mf2,... vsetvl e64,m1,... into

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p ()

https://gcc.gnu.org/g:45a9ae5a909c9320200984659ef6cd4e95af4f60 commit 45a9ae5a909c9320200984659ef6cd4e95af4f60 Author: Artemiy Volkov Date: Sat Jul 19 08:03:02 2025 -0600 [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p () > A number of folks have had thei

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_ceil auto vect

https://gcc.gnu.org/g:86afee58c9bd5b102292aa174192fd6aea21e17d commit 86afee58c9bd5b102292aa174192fd6aea21e17d Author: Pan Li Date: Wed Jul 16 21:40:14 2025 +0800 RISC-V: Support RVVDImode for avg3_ceil auto vect Like the avg3_floor pattern, the avg3_ceil has the similar issue

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_floor auto vect

https://gcc.gnu.org/g:6e7869a9d90fd88e8ef9053a0734403b5ef15da8 commit 6e7869a9d90fd88e8ef9053a0734403b5ef15da8 Author: Pan Li Date: Tue Jul 15 09:45:05 2025 +0800 RISC-V: Support RVVDImode for avg3_floor auto vect The avg3_floor pattern leverage the add and shift rtl with the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for rv32 SAT_MUL from uint64

https://gcc.gnu.org/g:48a48defbec1c453bd4bd4ebaf7bf52b47f9bfb0 commit 48a48defbec1c453bd4bd4ebaf7bf52b47f9bfb0 Author: Pan Li Date: Fri Jul 11 08:58:31 2025 +0800 RISC-V: Add testcase for rv32 SAT_MUL from uint64 Add the run and asm testcase for rv32 SAT_MUL, widen mul from ui

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

https://gcc.gnu.org/g:978dc3441f0b2691c49ae8a94c8c260d2ddfc79d commit 978dc3441f0b2691c49ae8a94c8c260d2ddfc79d Author: Umesh Kalappa Date: Tue Jul 15 10:35:44 2025 -0600 [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Updated the test for rv32 accordingly and no regress fo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12

https://gcc.gnu.org/g:2f74422509a02739fd4fb7445817662951380a50 commit 2f74422509a02739fd4fb7445817662951380a50 Author: panciyan Date: Thu Jul 10 06:54:26 2025 + RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12 This patch adds testcase for form11 and form12

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:dc15a0c504e786f72dbaf60f8bbefe023763f575 commit dc15a0c504e786f72dbaf60f8bbefe023763f575 Author: Paul-Antoine Arras Date: Mon Jul 14 06:10:44 2025 -0600 [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] This pattern enables

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Detect new fusions for RISC-V

https://gcc.gnu.org/g:566bdaf77d1ad3178ee9bc6f8f6b8d35495f0c70 commit 566bdaf77d1ad3178ee9bc6f8f6b8d35495f0c70 Author: Daniel Barboza Date: Thu Jul 10 07:28:38 2025 -0600 [RISC-V] Detect new fusions for RISC-V This is primarily Daniel's work... He's chasing things in QEMU & LLVM

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISCV: Remove the v extension requirement for sat scalar run test

https://gcc.gnu.org/g:13eb06828a89f8fd76780b5a6263109895ca4490 commit 13eb06828a89f8fd76780b5a6263109895ca4490 Author: Pan Li Date: Wed Jul 9 10:40:52 2025 +0800 RISCV: Remove the v extension requirement for sat scalar run test The sat scalar run test should not require the v exte

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Make zero-stride load broadcast a tunable.

https://gcc.gnu.org/g:e12eda61b04e42a13bc753d98ab069008f2b0152 commit e12eda61b04e42a13bc753d98ab069008f2b0152 Author: Robin Dapp Date: Thu Jul 10 09:41:48 2025 +0200 RISC-V: Make zero-stride load broadcast a tunable. This patch makes the zero-stride load broadcast idiom dependent

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:ff641fee6121df08d657e5dc81940d63bc221d0c commit ff641fee6121df08d657e5dc81940d63bc221d0c Author: Pan Li Date: Mon Jul 7 11:17:00 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost

https://gcc.gnu.org/g:c7336b0ec09a2c150f5fa9d03841b5856b4f5fa6 commit c7336b0ec09a2c150f5fa9d03841b5856b4f5fa6 Author: Pan Li Date: Mon Jul 7 11:07:11 2025 +0800 RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:ad153da83136351fba6a62dbfacb65787c6832db commit ad153da83136351fba6a62dbfacb65787c6832db Author: Pan Li Date: Mon Jul 7 11:13:15 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests

https://gcc.gnu.org/g:2bf583acb7ef0df77880f44d08b6a5d0091be4ee commit 2bf583acb7ef0df77880f44d08b6a5d0091be4ee Author: Paul-Antoine Arras Date: Wed Jul 9 08:36:24 2025 -0600 [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests zvfh is not enabled at the testsuite lev

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB

https://gcc.gnu.org/g:c26128cc02c4468d5ff869e4648b128f8171d7b0 commit c26128cc02c4468d5ff869e4648b128f8171d7b0 Author: Ciyan Pan Date: Wed Jul 9 08:31:25 2025 -0600 [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB This patch adjust test data for unsigned vector SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector

https://gcc.gnu.org/g:063463c7412c48702c639f4bea39cfc0fa853b71 commit 063463c7412c48702c639f4bea39cfc0fa853b71 Author: Jeff Law Date: Wed Jul 9 05:23:34 2025 -0600 [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector AVL propagation currently assumes that it c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

https://gcc.gnu.org/g:551a1070e10a07ad679aa2a754933a7eb72605f9 commit 551a1070e10a07ad679aa2a754933a7eb72605f9 Author: Pan Li Date: Tue Jul 8 10:46:29 2025 +0800 RISC-V: Disable uint128_t testcase of SAT_MUL when rv32 The rv32 doesn't support __uint128, and then we will have e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Do not use vsetivli for THeadVector.

https://gcc.gnu.org/g:cc172c415c410d3a9697c858261f0ef412d9cd5f commit cc172c415c410d3a9697c858261f0ef412d9cd5f Author: Robin Dapp Date: Tue Jul 8 11:35:12 2025 +0200 RISC-V: Do not use vsetivli for THeadVector. In emit_vlmax_insn_lra we use a vsetivli for an immediate AVL. XTH

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore non-types in builtin function hash.

https://gcc.gnu.org/g:cee886d8332c31d15d8d6c71ca786ce8377a949d commit cee886d8332c31d15d8d6c71ca786ce8377a949d Author: Robin Dapp Date: Tue Jul 8 11:17:41 2025 +0200 RISC-V: Ignore non-types in builtin function hash. If a user passes a string that doesn't represent a variable we s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed][RISC-V] Fix testsuite fallout from check-function-bodies change

https://gcc.gnu.org/g:70ef784e6e8930a58f22c875a2675081f0654124 commit 70ef784e6e8930a58f22c875a2675081f0654124 Author: Jeff Law Date: Mon Jul 7 20:42:04 2025 -0600 [committed][RISC-V] Fix testsuite fallout from check-function-bodies change Minor fallout from HJ's recent change to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:dd13f632fc0ca4aad71e5a3711be364f75ce0451 commit dd13f632fc0ca4aad71e5a3711be364f75ce0451 Author: Pan Li Date: Thu Jul 3 17:17:28 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:c2407a35f8a9686f02045c96a243481d57631c22 commit c2407a35f8a9686f02045c96a243481d57631c22 Author: Pan Li Date: Wed Jul 2 10:52:25 2025 +0800 RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t Add run and tree-optimized check for unsigned scalar

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Implement unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:f350a0c6e57556cc0daf1983acc9311bc202cabf commit f350a0c6e57556cc0daf1983acc9311bc202cabf Author: Pan Li Date: Wed Jul 2 10:35:10 2025 +0800 RISC-V: Implement unsigned scalar SAT_MUL from uint128_t This patch would like to implement the SAT_MUL scalar unsigned

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:9a7ef485a1610304ffa131fb620f62fc75e63de5 commit 9a7ef485a1610304ffa131fb620f62fc75e63de5 Author: Pan Li Date: Thu Jul 3 17:16:21 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add basic instrumentation to fusion detection

https://gcc.gnu.org/g:34058e1b5354577d15234578042892469133a405 commit 34058e1b5354577d15234578042892469133a405 Author: Shreya Munnangi Date: Thu Jul 3 21:03:03 2025 -0600 [RISC-V] Add basic instrumentation to fusion detection We were looking to evaluate some changes from Artemiy t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost

https://gcc.gnu.org/g:7adca553661eb0c81c865b61d827577dfd1439a7 commit 7adca553661eb0c81c865b61d827577dfd1439a7 Author: Pan Li Date: Thu Jul 3 17:07:44 2025 +0800 RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Refactor record_function_versions.

https://gcc.gnu.org/g:6178f49509e301dbde9c3210a4842fa297612ac1 commit 6178f49509e301dbde9c3210a4842fa297612ac1 Author: Alfie Richards Date: Thu Mar 27 14:12:06 2025 + Refactor record_function_versions. Renames record_function_versions to add_function_version, and make it e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2

https://gcc.gnu.org/g:564db692f7478d8cf8ca7d9a63f1aeea023e0e7c commit 564db692f7478d8cf8ca7d9a63f1aeea023e0e7c Author: panciyan Date: Tue Jun 24 09:58:14 2025 +0800 RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2 This patch adds testcase for form2, as shown below:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates

https://gcc.gnu.org/g:93272b7f745184185ce433a24712b1356fe17272 commit 93272b7f745184185ce433a24712b1356fe17272 Author: Jeff Law Date: Thu Jul 3 06:44:31 2025 -0600 [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates A number of folks have had their

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

https://gcc.gnu.org/g:334c22fde20435a7510ba4448724c1e6830f2f5c commit 334c22fde20435a7510ba4448724c1e6830f2f5c Author: Dimitar Dimitrov Date: Fri Jun 20 20:57:15 2025 +0300 RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs Some test cases explicitly set -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

https://gcc.gnu.org/g:b86b8dc70d54702694917ede31221402ed8ccff3 commit b86b8dc70d54702694917ede31221402ed8ccff3 Author: Alexey Merzlyakov Date: Wed Jul 2 11:29:00 2025 -0600 [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] It corrects the shift type

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:356827b2868ca5fe33ca61d24f19c46f671b095b commit 356827b2868ca5fe33ca61d24f19c46f671b095b Author: Pan Li Date: Fri Jun 27 09:09:08 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:0077e94fb0b6c8a47aa9ff8939e1a79d46aa59a3 commit 0077e94fb0b6c8a47aa9ff8939e1a79d46aa59a3 Author: Pan Li Date: Fri Jun 27 09:06:38 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test due to cost model change

https://gcc.gnu.org/g:f72695c3adb8b5fbfffb925c8d41d91ffeee908f commit f72695c3adb8b5fbfffb925c8d41d91ffeee908f Author: Pan Li Date: Fri Jun 27 11:35:18 2025 +0800 RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cost of vx to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

https://gcc.gnu.org/g:2fddfd43e4d69c52b83d32504997daf893b31c18 commit 2fddfd43e4d69c52b83d32504997daf893b31c18 Author: Pan Li Date: Fri Jun 27 09:02:03 2025 +0800 RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore -Oz for most rvv testcase [NFC]

https://gcc.gnu.org/g:ad0f9e60f428440e5adc92c09bb3aea4f73d2587 commit ad0f9e60f428440e5adc92c09bb3aea4f73d2587 Author: Kito Cheng Date: Mon Jun 30 14:18:07 2025 +0800 RISC-V: Ignore -Oz for most rvv testcase [NFC] Most testcase in rvv folder already ignore -Oz, but some of them

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659

https://gcc.gnu.org/g:13c275d298a124c134c7532aaabb7bbc66d08c1e commit 13c275d298a124c134c7532aaabb7bbc66d08c1e Author: Kito Cheng Date: Tue Jun 17 16:20:19 2025 +0800 RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659] gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Primary vector pipeline model for sifive 7 series

https://gcc.gnu.org/g:e0b6c515e36b9e472f1a70f72748050ad3076d01 commit e0b6c515e36b9e472f1a70f72748050ad3076d01 Author: Kito Cheng Date: Thu Jun 19 14:31:42 2025 +0800 RISC-V: Primary vector pipeline model for sifive 7 series This commit introduces a primary vector pipeline model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the function bitmap_union_of_preds_with_entry

https://gcc.gnu.org/g:d62850c7c8be04f705ce143bc951cd0c8a35ce81 commit d62850c7c8be04f705ce143bc951cd0c8a35ce81 Author: Jin Ma Date: Sat Jun 28 19:55:00 2025 +0800 RISC-V: Refactor the function bitmap_union_of_preds_with_entry The current implementation of this function is somewhat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:3de8682d4a7482a5c37cfe9c9b44a3cfa5923dae commit 3de8682d4a7482a5c37cfe9c9b44a3cfa5923dae Author: Paul-Antoine Arras Date: Thu Jun 26 13:20:49 2025 + RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pa

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pipeline-checker script

https://gcc.gnu.org/g:03d4fda270410aa5aeb9dafe9fd67213bb273b1f commit 03d4fda270410aa5aeb9dafe9fd67213bb273b1f Author: Kito Cheng Date: Thu Jun 26 17:21:27 2025 +0800 RISC-V: Add pipeline-checker script Pipeline checker utility for RISC-V architecture that validates processor

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking

https://gcc.gnu.org/g:cb2c306e66571238cddced942ddb8b98d8fb commit cb2c306e66571238cddced942ddb8b98d8fb Author: Jeff Law Date: Fri Jun 27 07:00:15 2025 -0600 [RISC-V][PR target/119971] Avoid losing shift count masking Fix typo spotted by Bernhard Reutner-Fischer.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix build issue

https://gcc.gnu.org/g:3293115d939b25b2a5ebf445c82fb5117fc6c9bb commit 3293115d939b25b2a5ebf445c82fb5117fc6c9bb Author: Kito Cheng Date: Thu Jun 26 14:35:47 2025 +0800 RISC-V: Fix build issue Apparently I forgot to squash this fix into the previous commit before I push...

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828]

https://gcc.gnu.org/g:f7e693eb3a3a3561c4ff638940fba4c90d16950b commit f7e693eb3a3a3561c4ff638940fba4c90d16950b Author: Paul-Antoine Arras Date: Wed Jun 25 16:42:00 2025 + RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828] This is a followup to 92e

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