[gcc/aoliva/heads/testbase] (415 commits) libstdc++: Remove blank line from bits/unique_ptr.h

The branch 'aoliva/heads/testbase' was updated to point to: 153279208546... libstdc++: Remove blank line from bits/unique_ptr.h It previously pointed to: d94eb26871d7... [arm] require armv7 support for [PR120424] Diff: Summary of changes (added commits): ---

[gcc r16-3843] target.def: Properly mark up __cxa_atexit as code

https://gcc.gnu.org/g:8c23566d94e63243ee259290926c6dd4073a3893 commit r16-3843-g8c23566d94e63243ee259290926c6dd4073a3893 Author: Gerald Pfeifer Date: Sun Sep 14 01:06:51 2025 +0200 target.def: Properly mark up __cxa_atexit as code gcc: * target.def (dtors_from_cxa_atex

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Suppression set_dtype_if_unallocated

https://gcc.gnu.org/g:93dbd09fceb543ca2474efcc6d4fcc68b33f8eeb commit 93dbd09fceb543ca2474efcc6d4fcc68b33f8eeb Author: Mikael Morin Date: Sun Aug 10 11:03:57 2025 +0200 Suppression set_dtype_if_unallocated Extraction gfc_descriptor_set_dtype_if_unallocated Sauvegarde

[gcc(refs/users/aoliva/heads/testme)] [aarch64] [testsuite] disable PIE for nonlocal_goto sme tests

https://gcc.gnu.org/g:12da79de1238fe22719860a7b02a4dfb997f6853 commit 12da79de1238fe22719860a7b02a4dfb997f6853 Author: Alexandre Oliva Date: Wed Sep 10 19:59:14 2025 -0300 [aarch64] [testsuite] disable PIE for nonlocal_goto sme tests When an aarch64 toolchain is configured with --

[gcc(refs/users/aoliva/heads/testme)] [ppc] [vxworks] allow code model selection

https://gcc.gnu.org/g:48850dad88e8de7b9de905bc38627177e465cfd7 commit 48850dad88e8de7b9de905bc38627177e465cfd7 Author: Alexandre Oliva Date: Wed Sep 10 19:58:49 2025 -0300 [ppc] [vxworks] allow code model selection Bring code model selection logic to vxworks.h as well. fo

[gcc(refs/users/aoliva/heads/testme)] [ira] avoid resetting ira_reg_equiv for function invariants

https://gcc.gnu.org/g:05a64cd677c9fd2460fc675284275848a7c5a356 commit 05a64cd677c9fd2460fc675284275848a7c5a356 Author: Alexandre Oliva Date: Wed Sep 10 19:59:20 2025 -0300 [ira] avoid resetting ira_reg_equiv for function invariants An aarch64 toolchain built with --enable-default-

[gcc(refs/users/aoliva/heads/testme)] [ppc] adjust configure test for large TOC support

https://gcc.gnu.org/g:8c04e02bd20040c47b2f6317b2145a12e63326b1 commit 8c04e02bd20040c47b2f6317b2145a12e63326b1 Author: Alexandre Oliva Date: Wed Sep 10 19:58:35 2025 -0300 [ppc] adjust configure test for large TOC support The use of the TLS register in a TOC/GOT address computatio

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for avg_floor vaadd implementation

https://gcc.gnu.org/g:9ee44a0aa36c3e15b2eb6a6a987459be0cf7fc26 commit 9ee44a0aa36c3e15b2eb6a6a987459be0cf7fc26 Author: Pan Li Date: Tue May 27 10:27:01 2025 +0800 RISC-V: Add test cases for avg_floor vaadd implementation Add asm and run testcase for avg_floor vaadd implementation.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost

https://gcc.gnu.org/g:9b8b257bf62ef99c9960864164eccfa60a9f8cf0 commit 9b8b257bf62ef99c9960864164eccfa60a9f8cf0 Author: Pan Li Date: Fri May 23 13:22:35 2025 +0800 RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost This patch would like to combine the vec_duplicate + vo

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Extraction gfc_set_pdt_array_descriptor

https://gcc.gnu.org/g:680ce9db24c39f5799c3f22db93f1ecb4cc5f1d9 commit 680ce9db24c39f5799c3f22db93f1ecb4cc5f1d9 Author: Mikael Morin Date: Thu Jul 31 12:34:22 2025 +0200 Extraction gfc_set_pdt_array_descriptor Diff: --- gcc/fortran/trans-array.cc | 62 +---

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Refactor get_descr_dim_comp

https://gcc.gnu.org/g:8fda392ae9a8d7f9fb730ec6bf6f4de6511267bb commit 8fda392ae9a8d7f9fb730ec6bf6f4de6511267bb Author: Mikael Morin Date: Wed Aug 6 14:41:41 2025 +0200 Refactor get_descr_dim_comp Diff: --- gcc/fortran/trans-descriptor.cc | 17 ++--- 1 file changed, 6 insertio

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Correction ICE évaluation adresse

https://gcc.gnu.org/g:bef04edec0a6debb12aff1c9d0e0492ee24f7408 commit bef04edec0a6debb12aff1c9d0e0492ee24f7408 Author: Mikael Morin Date: Fri Aug 29 20:05:33 2025 +0200 gimple-simulate: Correction ICE évaluation adresse Diff: --- gcc/gimple-simulate.cc | 60 ++

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] riscv: testsuite: Fix misalignment check.

https://gcc.gnu.org/g:cce39329cefe85a0e83c6238ec38f57bfb011b49 commit cce39329cefe85a0e83c6238ec38f57bfb011b49 Author: Robin Dapp Date: Wed Jul 2 10:28:57 2025 +0200 riscv: testsuite: Fix misalignment check. This fixes a thinko in the misalignment check. If we want to check for

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Retour en arrière partiel eoshift0.c

https://gcc.gnu.org/g:c08d5420cfdaa60c23a91b2bb2915277a7bb6918 commit c08d5420cfdaa60c23a91b2bb2915277a7bb6918 Author: Mikael Morin Date: Sat Sep 13 21:07:09 2025 +0200 Retour en arrière partiel eoshift0.c Diff: --- libgfortran/intrinsics/eoshift0.c | 33 -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reuse test name for vx combine test data [NFC]

https://gcc.gnu.org/g:441da7e7ba6bec007b77438a6d4896c73531a250 commit 441da7e7ba6bec007b77438a6d4896c73531a250 Author: Pan Li Date: Tue May 13 22:54:17 2025 +0800 RISC-V: Reuse test name for vx combine test data [NFC] For run test, we have a name like add/sub to indicate the t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:5cf4aac629a087145136738c19cdb13b06bfc2f1 commit 5cf4aac629a087145136738c19cdb13b06bfc2f1 Author: Pan Li Date: Sun May 11 16:27:48 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run test for vec_

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V

https://gcc.gnu.org/g:68468028decb7b47f9b345c21169bf3b7331bec8 commit 68468028decb7b47f9b345c21169bf3b7331bec8 Author: Shreya Munnangi Date: Tue May 6 06:38:00 2025 -0600 [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V This is Shreya's next chunk of work. Whe

[gcc] Deleted branch 'mikael/heads/refactor_descriptor_v08' in namespace 'refs/users'

The branch 'mikael/heads/refactor_descriptor_v08' in namespace 'refs/users' was deleted. It previously pointed to: 755372267d11... Régénération fichiers générés Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ---

[gcc(refs/users/meissner/heads/work221-sha)] PR target/117251: Improve vector andc to vector andc fusion

https://gcc.gnu.org/g:4f61cad5a9349130619fc99b7b3bac203826ffe3 commit 4f61cad5a9349130619fc99b7b3bac203826ffe3 Author: Michael Meissner Date: Mon Sep 8 15:14:57 2025 -0400 PR target/117251: Improve vector andc to vector andc fusion See the following post for a complete explanation

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode

https://gcc.gnu.org/g:1180dc9249b533b07043d39b37bcbf97e29e1b4d commit 1180dc9249b533b07043d39b37bcbf97e29e1b4d Author: Pan Li Date: Mon Jul 21 09:06:52 2025 +0800 RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode This patch would like to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016]

https://gcc.gnu.org/g:93b0c20e9dbe422320c9b4c46bd508ad520ece87 commit 93b0c20e9dbe422320c9b4c46bd508ad520ece87 Author: Alexey Merzlyakov Date: Fri Apr 18 06:45:10 2025 -0600 [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016] It fixes one of the PR1

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:a7b8a3b2569b29d2da7be13deae6802bd3a2cef2 commit a7b8a3b2569b29d2da7be13deae6802bd3a2cef2 Author: Pan Li Date: Fri May 23 13:26:41 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Enable more if-conversion on RISC-V

https://gcc.gnu.org/g:cd4527f37ff93dd1f889f40691de73940bbe7c33 commit cd4527f37ff93dd1f889f40691de73940bbe7c33 Author: Jeff Law Date: Mon Jun 9 06:55:21 2025 -0600 [RISC-V] Enable more if-conversion on RISC-V Another czero related adjustment. This time in costing of conditional m

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Sauvegarde

https://gcc.gnu.org/g:f4f692cbe2df5eada3106860109835a6ea68c1ba commit f4f692cbe2df5eada3106860109835a6ea68c1ba Author: Mikael Morin Date: Thu Sep 4 17:10:58 2025 +0200 gimple-simulate: Sauvegarde Diff: --- gcc/gimple-simulate.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) di

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost

https://gcc.gnu.org/g:782289618f4dfdaddc66f89fdaecd2eef8f8dab8 commit 782289618f4dfdaddc66f89fdaecd2eef8f8dab8 Author: Pan Li Date: Tue Jun 17 10:00:54 2025 +0800 RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Correction cshift0.m4

https://gcc.gnu.org/g:7e427d335629ee19bb97f0aa63c776123692cff4 commit 7e427d335629ee19bb97f0aa63c776123692cff4 Author: Mikael Morin Date: Sat Sep 13 20:37:07 2025 +0200 Correction cshift0.m4 Retour en arrière cshift0 Remodif cshift0.m4 Réapplication modifs cshift

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Régénération fichiers générés

https://gcc.gnu.org/g:ebe1140a19e6784e807987e88d042faca7f55a05 commit ebe1140a19e6784e807987e88d042faca7f55a05 Author: Mikael Morin Date: Sat Sep 13 20:37:29 2025 +0200 Régénération fichiers générés Régénération fichiers générés Régénération fichiers générés Diff: --- l

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:69d67f108494760f781b0e0ba93ba0af00d4c04a commit 69d67f108494760f781b0e0ba93ba0af00d4c04a Author: yulong Date: Tue Apr 29 21:12:03 2025 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. This commit adds testcases for Xsfvcp. Co-Auth

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS

https://gcc.gnu.org/g:0b7aff4d0a4ff527e25f72b84f9c8d349f32ee38 commit 0b7aff4d0a4ff527e25f72b84f9c8d349f32ee38 Author: Zhijin Zeng Date: Mon Apr 28 09:24:16 2025 +0800 RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS SIBCALL_REGS/JALR_REGS are also subset of GR_REGS and n

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659

https://gcc.gnu.org/g:05aa2397bf8b685df15ebd19535737db1ce196f6 commit 05aa2397bf8b685df15ebd19535737db1ce196f6 Author: Kito Cheng Date: Tue Jun 17 16:20:19 2025 +0800 RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659] gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Zbb extension sext testcase.

https://gcc.gnu.org/g:99fdaa3ac2466509917a147204d1effbc82751b5 commit 99fdaa3ac2466509917a147204d1effbc82751b5 Author: Jiawei Date: Tue Sep 2 07:51:54 2025 -0600 RISC-V: Add Zbb extension sext testcase. This patch update RISC-V Zba extension 'sext' instructions generation. Sup

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve sequences to generate -1, 1 in some cases.

https://gcc.gnu.org/g:3f414c7a6dceb85230c58227a48f67bab6d23756 commit 3f414c7a6dceb85230c58227a48f67bab6d23756 Author: Jeff Law Date: Thu Jun 5 06:17:25 2025 -0600 [RISC-V] Improve sequences to generate -1, 1 in some cases. This patch has a minor improvement to if-converted sequen

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

https://gcc.gnu.org/g:701108ecdc13322b7fff54bdde1b42d416b31138 commit 701108ecdc13322b7fff54bdde1b42d416b31138 Author: Dimitar Dimitrov Date: Fri Jun 20 20:57:15 2025 +0300 RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs Some test cases explicitly set -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add basic instrumentation to fusion detection

https://gcc.gnu.org/g:67e71a6b4710818d2da06c2dc6545d0d51585178 commit 67e71a6b4710818d2da06c2dc6545d0d51585178 Author: Shreya Munnangi Date: Thu Jul 3 21:03:03 2025 -0600 [RISC-V] Add basic instrumentation to fusion detection We were looking to evaluate some changes from Artemiy t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for avg_ceil vaadd implementation

https://gcc.gnu.org/g:4c37e8960e7850f1495424b8732d88092b4045ef commit 4c37e8960e7850f1495424b8732d88092b4045ef Author: Pan Li Date: Thu May 29 21:33:44 2025 +0800 RISC-V: Add test cases for avg_ceil vaadd implementation Add asm and run testcase for avg_ceil vaadd implementation.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164]

https://gcc.gnu.org/g:d901e45585dc224c4c55c21ae3ad8fa1601c06f0 commit d901e45585dc224c4c55c21ae3ad8fa1601c06f0 Author: Vineet Gupta Date: Sun Jun 8 14:55:01 2025 -0700 RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164] FRM mode switching state machine has DY

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vrem.vx combine

https://gcc.gnu.org/g:75e94f9a228f228412aa9781a708addca967c4a7 commit 75e94f9a228f228412aa9781a708addca967c4a7 Author: Pan Li Date: Sun Jun 8 16:50:52 2025 +0800 RISC-V: Reconcile the existing test for vrem.vx combine Some existing vrem related test need some adjust for the as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Infrastructure of synthesizing logical AND with constant

https://gcc.gnu.org/g:afd52ccf7c880de82e7bf00bcfcfa9ab44168902 commit afd52ccf7c880de82e7bf00bcfcfa9ab44168902 Author: Shreya Munnangi Date: Tue May 20 20:15:42 2025 -0600 [RISC-V] Infrastructure of synthesizing logical AND with constant So this is the next step on the path to mvc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support CPUs in -march.

https://gcc.gnu.org/g:eb8bd08fea74d201c01340cff41edf1137c5be2b commit eb8bd08fea74d201c01340cff41edf1137c5be2b Author: Robin Dapp Date: Thu May 8 09:51:45 2025 +0200 RISC-V: Support CPUs in -march. This patch allows an -march string like -march=sifive-p670 in o

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

https://gcc.gnu.org/g:cc441a50e1e193ab285582903eb0ba0fc8961ae9 commit cc441a50e1e193ab285582903eb0ba0fc8961ae9 Author: Siarhei Volkau Date: Thu May 22 08:52:17 2025 -0600 [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32 Patch is originally from Siarhei Volkau .

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

https://gcc.gnu.org/g:7854069c14a4ae986654576dd3e11617256fa7fa commit 7854069c14a4ae986654576dd3e11617256fa7fa Author: Kito Cheng Date: Mon May 12 14:36:07 2025 +0800 RISC-V: Add new operand constraint: cR This commit introduces a new operand constraint `cR` for the RISC-V arc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Zilsd code gen

https://gcc.gnu.org/g:02bfc18462159489f176430094389808ecb4e4e2 commit 02bfc18462159489f176430094389808ecb4e4e2 Author: Kito Cheng Date: Mon May 12 02:38:39 2025 -0700 RISC-V: Support Zilsd code gen This commit adds the code gen support for Zilsd, which is a newly added extensi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]

https://gcc.gnu.org/g:c8b097176b496800d6b164c37400bb23b46fc883 commit c8b097176b496800d6b164c37400bb23b46fc883 Author: Kito Cheng Date: Mon May 5 10:16:14 2025 +0800 RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC] Tweak the formatting of the genrvv-type-indexer.cc file

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix some dynamic LMUL costing.

https://gcc.gnu.org/g:796346ee4edf5cce7714f303435e11088d5b5959 commit 796346ee4edf5cce7714f303435e11088d5b5959 Author: Robin Dapp Date: Fri Feb 7 15:42:28 2025 +0100 RISC-V: Fix some dynamic LMUL costing. With all-SLP we annotate statements slightly differently. This patch us

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost

https://gcc.gnu.org/g:5b1ded94d5613ca8087547b6d32d594c0414b92e commit 5b1ded94d5613ca8087547b6d32d594c0414b92e Author: Pan Li Date: Tue May 20 15:00:15 2025 +0800 RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost This patch would like to combine the vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:95e14bfe73ce665d6601c1fe4015dc4c7374e128 commit 95e14bfe73ce665d6601c1fe4015dc4c7374e128 Author: Pan Li Date: Mon Apr 28 20:35:09 2025 +0800 RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned integer SAT

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add augmented hypervisor series extensions.

https://gcc.gnu.org/g:4c43ce73a1c1573b6813f4ff1d2df3f46c218578 commit 4c43ce73a1c1573b6813f4ff1d2df3f46c218578 Author: Jiawei Date: Tue May 13 15:23:39 2025 +0800 RISC-V: Add augmented hypervisor series extensions. The augmented hypervisor series extensions 'sha'[1] is a new profi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RISC-V Profiles 20/22.

https://gcc.gnu.org/g:3c887420a1fd53fdf512dd9aef65c61627efd498 commit 3c887420a1fd53fdf512dd9aef65c61627efd498 Author: Jiawei Date: Sat May 10 20:25:52 2025 +0800 RISC-V: Support RISC-V Profiles 20/22. This patch introduces support for RISC-V Profiles RV20 and RV22 [1], enabli

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0

https://gcc.gnu.org/g:2ceff77897a6062d3e592c6d03b1f0cdd9e4d00e commit 2ceff77897a6062d3e592c6d03b1f0cdd9e4d00e Author: Pan Li Date: Sat May 3 10:40:20 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0 Add asm dump check and run test for vec_dup

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.

https://gcc.gnu.org/g:42b7dadd72fa4c11b4c274c3f4334ec623ce9c70 commit 42b7dadd72fa4c11b4c274c3f4334ec623ce9c70 Author: Dongyan Chen Date: Tue May 6 17:09:54 2025 -0600 [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions. This patch support sdtrig and ssstrict extens

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:e05923c4d7d5e76cee17536bfe1c985eaf2e2633 commit e05923c4d7d5e76cee17536bfe1c985eaf2e2633 Author: Pan Li Date: Thu May 8 11:19:11 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0 Add asm dump check and for vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:e60a6c0f15748304a8e815d5d4f684094e100089 commit e60a6c0f15748304a8e815d5d4f684094e100089 Author: yulong Date: Tue Apr 29 21:12:02 2025 +0800 RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. This version is same as v5, but rebase to trunk, send out

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] gimple-simulate: Propagation offset pour MEM_REF a l'interieur de tableau

https://gcc.gnu.org/g:a3b570a4b5ec6bb13ef4dbdb87a24c6a7aa850d2 commit a3b570a4b5ec6bb13ef4dbdb87a24c6a7aa850d2 Author: Mikael Morin Date: Sun Aug 31 18:18:46 2025 +0200 gimple-simulate: Propagation offset pour MEM_REF a l'interieur de tableau Diff: --- gcc/gimple-simulate.cc | 29 +++

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] fortran: Factor array descriptor references

https://gcc.gnu.org/g:736983d60bd44e5b8a78ea49fd04166a16fa51a8 commit 736983d60bd44e5b8a78ea49fd04166a16fa51a8 Author: Mikael Morin Date: Wed Jul 9 21:18:18 2025 +0200 fortran: Factor array descriptor references Regression tested on x86_64-pc-linux-gnu. OK for master?

[gcc(refs/users/mikael/heads/refactor_descriptor_v08)] Déplacemement plus de code gfc_set_pdt_array_descriptor

https://gcc.gnu.org/g:b47af53ec6195aceea7bebd364793c5a7f0cb115 commit b47af53ec6195aceea7bebd364793c5a7f0cb115 Author: Mikael Morin Date: Thu Jul 31 15:19:35 2025 +0200 Déplacemement plus de code gfc_set_pdt_array_descriptor Diff: --- gcc/fortran/trans-array.cc | 19

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix

https://gcc.gnu.org/g:33847ab70d3f4dee352ce14d1effc57d0d788e56 commit 33847ab70d3f4dee352ce14d1effc57d0d788e56 Author: Jeff Law Date: Sun May 4 08:28:56 2025 -0600 [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix The recent adjustment to more correc

[gcc(refs/users/meissner/heads/work221-bugs)] Merge commit 'refs/users/meissner/heads/work221-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work2

https://gcc.gnu.org/g:35e985b530ed62ff4c3e8d2f782743b3cea467a8 commit 35e985b530ed62ff4c3e8d2f782743b3cea467a8 Merge: 970421aeb875 001400b1deda Author: Michael Meissner Date: Mon Sep 8 14:13:11 2025 -0400 Merge commit 'refs/users/meissner/heads/work221-bugs' of git+ssh://gcc.gnu.org/git/g

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for unsigned scalar SAT_MUL form 4

https://gcc.gnu.org/g:8986a6777ab7535501d0aa9b372dafb3142b66b5 commit 8986a6777ab7535501d0aa9b372dafb3142b66b5 Author: Pan Li Date: Sun Aug 24 16:36:00 2025 +0800 RISC-V: Add test case for unsigned scalar SAT_MUL form 4 The form 4 of unsigned scalar SAT_MUL is covered in middle-ex

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:652f761c4482ffe9bb783d43d4a000eb03d29134 commit 652f761c4482ffe9bb783d43d4a000eb03d29134 Author: Pan Li Date: Mon Aug 4 09:54:34 2025 +0800 RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR cost 0, 1 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Regen riscv-ext.texi [NFC]

https://gcc.gnu.org/g:da17e1a5f29f6250cd127a3c54a3f1d661f0f8e8 commit da17e1a5f29f6250cd127a3c54a3f1d661f0f8e8 Author: Kito Cheng Date: Tue Jun 10 10:32:37 2025 +0800 RISC-V: Regen riscv-ext.texi [NFC] Regenerates the `riscv-ext.texi` file in the GCC documentation. gcc/Ch

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: fix an obvious build error

https://gcc.gnu.org/g:bcc6f4d88085b6ba4e90fac2941e9b2ee611b15a commit bcc6f4d88085b6ba4e90fac2941e9b2ee611b15a Author: Vineet Gupta Date: Tue May 20 14:15:53 2025 -0700 RISC-V: testsuite: fix an obvious build error For a non-multilib build, I see following errors. | FAIL:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

https://gcc.gnu.org/g:6791d38ad0ddc995fa5fd88768ee81daf3774709 commit 6791d38ad0ddc995fa5fd88768ee81daf3774709 Author: Kito Cheng Date: Wed May 7 20:59:15 2025 +0800 RISC-V: Introduce riscv_ext_info_t to hold extension metadata Define a new riscv_ext_info_t struct to aggregate all

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

https://gcc.gnu.org/g:da34ac6a25230a895ce04b7c5447d22353bc6e63 commit da34ac6a25230a895ce04b7c5447d22353bc6e63 Author: panciyan Date: Mon Jul 21 01:41:31 2025 + RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9 This patch adds testcase for form8 and form9, as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use helper function to get FPR to VR move cost

https://gcc.gnu.org/g:5143fa4a1e7ee766ca687438c6a3146a25e57372 commit 5143fa4a1e7ee766ca687438c6a3146a25e57372 Author: Paul-Antoine Arras Date: Wed May 28 12:09:22 2025 +0200 RISC-V: Use helper function to get FPR to VR move cost Since last patch introduced get_fr2vr_cost () to ge

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:78f75ae5f7a23e3b922426f52a5e754dfb9d7f16 commit 78f75ae5f7a23e3b922426f52a5e754dfb9d7f16 Author: Pan Li Date: Mon Jul 7 11:17:00 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB

https://gcc.gnu.org/g:474878af043e782b0a44a3bf95898fdaac21385d commit 474878af043e782b0a44a3bf95898fdaac21385d Author: Ciyan Pan Date: Wed Jul 9 08:31:25 2025 -0600 [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB This patch adjust test data for unsigned vector SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Detect new fusions for RISC-V

https://gcc.gnu.org/g:88c7db032d0e1226cb0438ace80fed0bdacbefa3 commit 88c7db032d0e1226cb0438ace80fed0bdacbefa3 Author: Daniel Barboza Date: Thu Jul 10 07:28:38 2025 -0600 [RISC-V] Detect new fusions for RISC-V This is primarily Daniel's work... He's chasing things in QEMU & LLVM

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:5bd4d8f3cde39a9631c34afefd2207dea732cd37 commit 5bd4d8f3cde39a9631c34afefd2207dea732cd37 Author: Paul-Antoine Arras Date: Mon Jul 14 06:10:44 2025 -0600 [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] This pattern enables

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

https://gcc.gnu.org/g:9d4fbe2f11c425388a1bd65f86bd4e3c0a00a481 commit 9d4fbe2f11c425388a1bd65f86bd4e3c0a00a481 Author: Pan Li Date: Thu Jun 5 11:04:33 2025 +0800 RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv The div of rvv has not such insn v2 = div (vec_dup (x), v1),

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Primary vector pipeline model for sifive 7 series

https://gcc.gnu.org/g:a1a50b7a1cca687a9ea6f1a6bbd1f3dfaa2f2d73 commit a1a50b7a1cca687a9ea6f1a6bbd1f3dfaa2f2d73 Author: Kito Cheng Date: Thu Jun 19 14:31:42 2025 +0800 RISC-V: Primary vector pipeline model for sifive 7 series This commit introduces a primary vector pipeline model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sscounterenw extension.

https://gcc.gnu.org/g:f1f241c15a7a1cf88e31bab97fafda500e3349c3 commit f1f241c15a7a1cf88e31bab97fafda500e3349c3 Author: Jiawei Date: Thu Jun 5 13:33:21 2025 +0800 RISC-V: Support Sscounterenw extension. Support the Sscounterenw extension, which allows writeable enables for any

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests

https://gcc.gnu.org/g:2fae7fb9cd00dc4ca4c73f2dde5462f9c90003b8 commit 2fae7fb9cd00dc4ca4c73f2dde5462f9c90003b8 Author: Paul-Antoine Arras Date: Wed Jul 9 08:36:24 2025 -0600 [PATCH] RISC-V: Enable zvfh for vector-scalar half-float run tests zvfh is not enabled at the testsuite lev

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:68c9a44074b3802da024c3f0616fd9a1b6bb1c9c commit 68c9a44074b3802da024c3f0616fd9a1b6bb1c9c Author: Pan Li Date: Thu Jul 3 17:16:21 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100]

https://gcc.gnu.org/g:a562773850695bd4a1bdcba00e32ecbb4f5f1472 commit a562773850695bd4a1bdcba00e32ecbb4f5f1472 Author: Paul-Antoine Arras Date: Mon May 12 14:42:24 2025 +0200 RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100] This pattern enables the combine pass (o

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates

https://gcc.gnu.org/g:6025fc8b50f97eddb3d3ce3ca8b24107ecca1260 commit 6025fc8b50f97eddb3d3ce3ca8b24107ecca1260 Author: Jeff Law Date: Thu Jul 3 06:44:31 2025 -0600 [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates A number of folks have had their

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding cost model for zilsd

https://gcc.gnu.org/g:8831a31c8ab1f0bc29e524bf23ad0ea3be6fbd17 commit 8831a31c8ab1f0bc29e524bf23ad0ea3be6fbd17 Author: Kito Cheng Date: Tue Jun 17 12:56:17 2025 +0800 RISC-V: Adding cost model for zilsd Motivation of this patch is we want to use ld/sd if possible when zilsd is

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:4dc4609253c32585102ea9bf96a5c1ccfbf4c00f commit 4dc4609253c32585102ea9bf96a5c1ccfbf4c00f Author: Pan Li Date: Mon Jun 9 16:35:47 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support -mcpu for XiangShan Kunminghu cpu.

https://gcc.gnu.org/g:1b143568696a60b7287d704c393dfcfd06f30f3e commit 1b143568696a60b7287d704c393dfcfd06f30f3e Author: Jiawei Date: Wed Jun 4 17:56:49 2025 +0800 RISC-V: Support -mcpu for XiangShan Kunminghu cpu. This patch adds support for the XiangShan Kunminghu CPU in GCC, allo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vdivu.vx combine

https://gcc.gnu.org/g:2babc2585bdbe17250eda473d3a0d5a7483cc948 commit 2babc2585bdbe17250eda473d3a0d5a7483cc948 Author: Pan Li Date: Fri Jun 6 10:03:50 2025 +0800 RISC-V: Reconcile the existing test for vdivu.vx combine Some existing vdiv related test need some adjust for the a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmadd.vv unsigned combine with GR2VR cost 0, 1 and 15

https://gcc.gnu.org/g:85965629e18bedd90dd3968ded8464ea650571ba commit 85965629e18bedd90dd3968ded8464ea650571ba Author: Pan Li Date: Tue Sep 2 13:31:40 2025 +0800 RISC-V: Add test for vec_duplicate + vmadd.vv unsigned combine with GR2VR cost 0, 1 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesperf ISA extension.

https://gcc.gnu.org/g:31b8d5c4fbc94fc291477dae86cba8e56633c6fc commit 31b8d5c4fbc94fc291477dae86cba8e56633c6fc Author: Kuan-Lin Chen Date: Wed Sep 3 16:52:49 2025 -0600 RISC-V: Add support for the XAndesperf ISA extension. This patch adds support for the XAndesperf ISA extension.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:7519537ddf83f0faf8d6c33a549bf7c1939637a4 commit 7519537ddf83f0faf8d6c33a549bf7c1939637a4 Author: Pan Li Date: Sun May 18 16:49:29 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.

https://gcc.gnu.org/g:9611a54c76b4b7c08aaacadb30a1cdfbf8e005b7 commit 9611a54c76b4b7c08aaacadb30a1cdfbf8e005b7 Author: Dongyan Chen Date: Wed May 21 21:46:52 2025 -0600 [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level. Failed testcases occurr

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:cb21a957db8fcf8f99629800c65d14b68995f902 commit cb21a957db8fcf8f99629800c65d14b68995f902 Author: Pan Li Date: Sun May 18 19:53:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:9cb277baac566ef946c02b82471593042ee3dcef commit 9cb277baac566ef946c02b82471593042ee3dcef Author: Pan Li Date: Sun May 11 16:32:51 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv-ext.def to generate target options and variables

https://gcc.gnu.org/g:2375a31746a195da9c026e22b4bc54eb59886d11 commit 2375a31746a195da9c026e22b4bc54eb59886d11 Author: Kito Cheng Date: Wed May 7 18:28:18 2025 +0800 RISC-V: Use riscv-ext.def to generate target options and variables Leverage the centralized riscv-ext.def definitio

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1

https://gcc.gnu.org/g:ce5cf7e86a13b7db8135a35f44d5f06e904acc19 commit ce5cf7e86a13b7db8135a35f44d5f06e904acc19 Author: Pan Li Date: Sat May 3 11:27:50 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1 Add asm dump check and for vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support for zilsd and zclsd extensions.

https://gcc.gnu.org/g:b5076801896ccc64af3bd4fe5d9ccc79cb068136 commit b5076801896ccc64af3bd4fe5d9ccc79cb068136 Author: Dongyan Chen Date: Mon Mar 17 22:23:18 2025 +0800 RISC-V: Support for zilsd and zclsd extensions. This patch support zilsd and zclsd[1] extensions. To enable

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:7188430d5d676e86721f0f68510f7186e0bd13bc commit 7188430d5d676e86721f0f68510f7186e0bd13bc Author: Kito Cheng Date: Wed May 7 21:27:20 2025 +0800 RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data Refactor extension flag handling by removing th

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

https://gcc.gnu.org/g:3ddefe74a828d3f6375960533a90a5dfbb7ca13b commit 3ddefe74a828d3f6375960533a90a5dfbb7ca13b Author: Dongyan Chen Date: Mon May 12 17:19:24 2025 +0800 RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions. This patch support ssnpm, smnpm, smmpm, sspm and

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

https://gcc.gnu.org/g:55d8883e50bd8afb763177347c791b32c59a5b52 commit 55d8883e50bd8afb763177347c791b32c59a5b52 Author: Pan Li Date: Sun May 11 16:20:28 2025 +0800 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Make end_sequence return the insn sequence

https://gcc.gnu.org/g:dbdc116ecf2ae8a33c9a6857bc6d03b6194803fc commit dbdc116ecf2ae8a33c9a6857bc6d03b6194803fc Author: Richard Sandiford Date: Fri May 16 13:24:01 2025 +0100 Make end_sequence return the insn sequence The start_sequence/end_sequence interface was a big improvement

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Separate the test running of rvv vx_vf

https://gcc.gnu.org/g:0ec8a282f30baeda195e501336c1c6842ccdf8b7 commit 0ec8a282f30baeda195e501336c1c6842ccdf8b7 Author: Pan Li Date: Thu May 8 10:00:50 2025 +0800 RISC-V: Separate the test running of rvv vx_vf The default test running in rvv.exp takes the -fno-vect-cost-model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:c3b76844e970680f22674ad94e4d9b154c0e73f2 commit c3b76844e970680f22674ad94e4d9b154c0e73f2 Author: Kito Cheng Date: Wed May 7 21:21:01 2025 +0800 RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data Consolidate implied-exten

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:0c8f5d9467007eef9050c17cb4904dbbad9402ea commit 0c8f5d9467007eef9050c17cb4904dbbad9402ea Author: Pan Li Date: Thu May 8 11:25:04 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2 Add asm dump check and for vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication

https://gcc.gnu.org/g:ac3346915131ff0dee42e9aa8e8d494dc5bf21f6 commit ac3346915131ff0dee42e9aa8e8d494dc5bf21f6 Author: Pan Li Date: Fri May 16 15:34:51 2025 +0800 RISC-V: Avoid scalar unsigned SAT_ADD test data duplication Some of the previous scalar unsigned SAT_ADD test data are

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new option --param=gpr2vr-cost= for rvv insn

https://gcc.gnu.org/g:b5353742ec381d1aa25e336d8717d212c5b243b2 commit b5353742ec381d1aa25e336d8717d212c5b243b2 Author: Pan Li Date: Tue May 6 16:26:06 2025 +0800 RISC-V: Add new option --param=gpr2vr-cost= for rvv insn During investigate the combine from vec_dup and vop.vv into

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] testsuite: Fix RISC-V arch-52.c format issue.

https://gcc.gnu.org/g:5e925dff5e87b86dfb7489ad7b6150e75e2d8aee commit 5e925dff5e87b86dfb7489ad7b6150e75e2d8aee Author: Jiawei Date: Mon May 12 13:23:50 2025 +0800 testsuite: Fix RISC-V arch-52.c format issue. Fix incorrect regular expression. gcc/testsuite/ChangeLog:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0

https://gcc.gnu.org/g:583ff95ed9b30a8d0374926511e040aaf9c16328 commit 583ff95ed9b30a8d0374926511e040aaf9c16328 Author: Pan Li Date: Wed May 7 20:48:40 2025 +0800 RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0 This patch would like to rename the VX_BINARY within CASE_0 su

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [V2][RISC-V] Synthesize more efficient IOR/XOR sequences

https://gcc.gnu.org/g:19ca071409104d08f76238c040ab2a0e21883f08 commit 19ca071409104d08f76238c040ab2a0e21883f08 Author: Shreya Munnangi Date: Sat May 10 07:18:33 2025 -0600 [V2][RISC-V] Synthesize more efficient IOR/XOR sequences So mvconst_internal's primary benefit is in constant

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