[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reorder insn cost match order to match corresponding expander match order

https://gcc.gnu.org/g:77bdff2732045dfd049cb8ab91c948514f444fcb commit 77bdff2732045dfd049cb8ab91c948514f444fcb Author: Patrick O'Neill Date: Tue Aug 20 11:38:20 2024 -0700 RISC-V: Reorder insn cost match order to match corresponding expander match order The corresponding expander

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vid const vector expander for non-npatterns size steps

https://gcc.gnu.org/g:3d0ae86388b8c89133386e9ee2c97ac8c75bf80a commit 3d0ae86388b8c89133386e9ee2c97ac8c75bf80a Author: Patrick O'Neill Date: Wed Aug 21 23:48:24 2024 -0700 RISC-V: Fix vid const vector expander for non-npatterns size steps Prior to this patch the expander would emi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support IMM for operand 1 of ussub pattern

https://gcc.gnu.org/g:a5bd5cc741a806106740fb10837dd6dacc630298 commit a5bd5cc741a806106740fb10837dd6dacc630298 Author: Pan Li Date: Mon Aug 26 15:58:52 2024 +0800 RISC-V: Support IMM for operand 1 of ussub pattern This patch would like to allow IMM for the operand 1 of ussub patte

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move helper functions above expand_const_vector

https://gcc.gnu.org/g:9d19855517b95a0205c795becab4c67b0c9eac7e commit 9d19855517b95a0205c795becab4c67b0c9eac7e Author: Patrick O'Neill Date: Mon Aug 19 12:40:14 2024 -0700 RISC-V: Move helper functions above expand_const_vector These subroutines will be used in expand_const_vector

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support IMM for operand 0 of ussub pattern

https://gcc.gnu.org/g:ffb7ed746bee04052b62b2d4601bc9992acb40bc commit ffb7ed746bee04052b62b2d4601bc9992acb40bc Author: Pan Li Date: Sat Aug 3 07:02:57 2024 + RISC-V: Support IMM for operand 0 of ussub pattern This patch would like to allow IMM for the operand 0 of ussub patter

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4

https://gcc.gnu.org/g:db1772fa10aecab5344bac705c60baaba71fd11c commit db1772fa10aecab5344bac705c60baaba71fd11c Author: Pan Li Date: Sun Aug 25 14:15:40 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4 This patch would like to add test cases for the unsigned v

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4

https://gcc.gnu.org/g:a2432f0bc14acc8bfed1f72728f2b8bf9b2f9744 commit a2432f0bc14acc8bfed1f72728f2b8bf9b2f9744 Author: Pan Li Date: Sun Aug 25 11:02:10 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix double mode under RV32 not utilize vf

https://gcc.gnu.org/g:93ef25c6f7366df397a985df569d12def715ee22 commit 93ef25c6f7366df397a985df569d12def715ee22 Author: demin.han Date: Sun Aug 25 15:53:58 2024 -0600 RISC-V: Fix double mode under RV32 not utilize vf Currently, some binops of vector vs double scalar under RV32 can'

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.

https://gcc.gnu.org/g:76ed0a7caacfc924d5ba67fc1eabc6446a8d8207 commit 76ed0a7caacfc924d5ba67fc1eabc6446a8d8207 Author: Xianmiao Qu Date: Sun Aug 25 11:22:21 2024 -0600 [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move. The previous patch: https://g

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Disable late-combine in another RISC-V test

https://gcc.gnu.org/g:12fb83c7f94ad3a2b73a940f045ab6ec70f87d8b commit 12fb83c7f94ad3a2b73a940f045ab6ec70f87d8b Author: Jeff Law Date: Sun Aug 25 07:24:56 2024 -0600 Disable late-combine in another RISC-V test Another test where the output was slightly twiddled by late-combine in w

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Fix assembly scan for RISC-V VLS tests

https://gcc.gnu.org/g:d95274bbd89eca93a94670d4688fa4b829cd commit d95274bbd89eca93a94670d4688fa4b829cd Author: Jeff Law Date: Sun Aug 25 07:16:50 2024 -0600 [committed] Fix assembly scan for RISC-V VLS tests Surya's IRA patch from June slightly improves the code we generat

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495].

https://gcc.gnu.org/g:0e8e9e768db6649899038cf4a0de2ad604cb4535 commit 0e8e9e768db6649899038cf4a0de2ad604cb4535 Author: Robin Dapp Date: Tue Aug 20 14:02:09 2024 +0200 optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495]. In get_best_extraction_insn we use

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Turn off late-combine for a few risc-v specific tests

https://gcc.gnu.org/g:ee54c9f75f443283801cc11eaec3d58ad85170b0 commit ee54c9f75f443283801cc11eaec3d58ad85170b0 Author: Jeff Law Date: Sun Aug 25 07:06:45 2024 -0600 Turn off late-combine for a few risc-v specific tests Just minor testsuite adjustments -- several of the shorten-mem

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use encoded nelts when calling repeating_sequence_p

https://gcc.gnu.org/g:3ee78b3342cbe83e3498fd0b355e57ff9a30966d commit 3ee78b3342cbe83e3498fd0b355e57ff9a30966d Author: Patrick O'Neill Date: Mon Aug 19 12:19:33 2024 -0700 RISC-V: Use encoded nelts when calling repeating_sequence_p repeating_sequence_p operates directly on the enc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Expand vec abs without masking.

https://gcc.gnu.org/g:57cc189f5f5b50711fd37ee08308157fec0033f9 commit 57cc189f5f5b50711fd37ee08308157fec0033f9 Author: Robin Dapp Date: Fri Aug 9 15:05:39 2024 +0200 RISC-V: Expand vec abs without masking. Standard abs synthesis during expand is max (a, -a). This expansion ha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow

https://gcc.gnu.org/g:9843c449d1ff93e0dc402f08eae0362302989049 commit 9843c449d1ff93e0dc402f08eae0362302989049 Author: Jeff Law Date: Thu Aug 22 12:48:49 2024 -0600 [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow The DF framework provides us a way to run data

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vector cfi notes for stack-clash protection

https://gcc.gnu.org/g:204928bdf68a333ff8ca232397fb6a29b91bbc6a commit 204928bdf68a333ff8ca232397fb6a29b91bbc6a Author: Raphael Moreira Zinsly Date: Wed Aug 21 18:08:54 2024 -0300 RISC-V: Fix vector cfi notes for stack-clash protection The stack-clash code is generating wrong cfi d

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

https://gcc.gnu.org/g:327021ed2a74817b2c9986e87358d84a0d921b00 commit 327021ed2a74817b2c9986e87358d84a0d921b00 Author: Pan Li Date: Wed Aug 21 17:57:47 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3 This patch would like to add test cases for the unsigned v

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2

https://gcc.gnu.org/g:c8eec5d1eb5db3ed9ec0a781fe94867f69d3 commit c8eec5d1eb5db3ed9ec0a781fe94867f69d3 Author: Pan Li Date: Wed Aug 21 17:43:12 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2 This patch would like to add test cases for the unsigned v

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]

https://gcc.gnu.org/g:f93c8ea4f748225910a1cb25e95adc081e0d7be7 commit f93c8ea4f748225910a1cb25e95adc081e0d7be7 Author: Pan Li Date: Tue Aug 20 21:08:23 2024 +0800 RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC] Fix one typo `sat_truc` to `sat_trunc`, as well as `SAT_TRUC`

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce

https://gcc.gnu.org/g:9660ade008244720fc3653865c7beaae09d6e3da commit 9660ade008244720fc3653865c7beaae09d6e3da Author: Jeff Law Date: Wed Aug 21 16:52:23 2024 -0600 [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce Another RTL checking failure in ext-dce. An easy one

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove testcase XFAIL

https://gcc.gnu.org/g:fa76531046b57a540ccf88a67e7636353dfe43e0 commit fa76531046b57a540ccf88a67e7636353dfe43e0 Author: Edwin Lu Date: Mon Aug 19 13:10:15 2024 -0700 RISC-V: Remove testcase XFAIL The testcase has been modified to include the -fwrapv flag which now causes the te

[gcc r15-3170] RISC-V: Fix double mode under RV32 not utilize vf

https://gcc.gnu.org/g:7f65c38ac1b18773d55c08d6ba920a798462b871 commit r15-3170-g7f65c38ac1b18773d55c08d6ba920a798462b871 Author: demin.han Date: Sun Aug 25 15:53:58 2024 -0600 RISC-V: Fix double mode under RV32 not utilize vf Currently, some binops of vector vs double scalar under

[gcc r15-3169] [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.

https://gcc.gnu.org/g:dba20679f1bf138ab5e61ad131b887db42083174 commit r15-3169-gdba20679f1bf138ab5e61ad131b887db42083174 Author: Xianmiao Qu Date: Sun Aug 25 11:22:21 2024 -0600 [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move. The previous patch:

[gcc r15-3161] Disable late-combine in another RISC-V test

https://gcc.gnu.org/g:70edccf88738ec204036e498a4a50c46e5e4f0c0 commit r15-3161-g70edccf88738ec204036e498a4a50c46e5e4f0c0 Author: Jeff Law Date: Sun Aug 25 07:24:56 2024 -0600 Disable late-combine in another RISC-V test Another test where the output was slightly twiddled by late-co

[gcc r15-3160] [committed] Fix assembly scan for RISC-V VLS tests

https://gcc.gnu.org/g:4c3485897d3e28ecfbe911f21f83fa047ee8b54b commit r15-3160-g4c3485897d3e28ecfbe911f21f83fa047ee8b54b Author: Jeff Law Date: Sun Aug 25 07:16:50 2024 -0600 [committed] Fix assembly scan for RISC-V VLS tests Surya's IRA patch from June slightly improves the code

[gcc r15-3159] Turn off late-combine for a few risc-v specific tests

https://gcc.gnu.org/g:ab9c4bb54e817948f1a55edfb0f1f0481e4046df commit r15-3159-gab9c4bb54e817948f1a55edfb0f1f0481e4046df Author: Jeff Law Date: Sun Aug 25 07:06:45 2024 -0600 Turn off late-combine for a few risc-v specific tests Just minor testsuite adjustments -- several of the s

[gcc r15-3095] [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow

https://gcc.gnu.org/g:c9377734b798d8d311dfd3a5618dc49407703b93 commit r15-3095-gc9377734b798d8d311dfd3a5618dc49407703b93 Author: Jeff Law Date: Thu Aug 22 12:48:49 2024 -0600 [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow The DF framework provides us a way t

[gcc r15-3074] [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce

https://gcc.gnu.org/g:cdc9cd4afe8949276a0c50215eb7f23e2086044f commit r15-3074-gcdc9cd4afe8949276a0c50215eb7f23e2086044f Author: Jeff Law Date: Wed Aug 21 16:52:23 2024 -0600 [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce Another RTL checking failure in ext-dce. A

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

https://gcc.gnu.org/g:3cbfc97902cc85ef0591c77bbdb3427447db1a59 commit 3cbfc97902cc85ef0591c77bbdb3427447db1a59 Author: Pan Li Date: Tue Jul 23 11:18:48 2024 +0800 RISC-V: Implement the quad and oct .SAT_TRUNC for scalar This patch would like to implement the quad and oct .SAT_TRUN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc

https://gcc.gnu.org/g:540c6b796fe3b6efb51a788cae511ef15b62801c commit 540c6b796fe3b6efb51a788cae511ef15b62801c Author: Jeff Law Date: Sun Aug 18 16:55:52 2024 -0600 [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc This fixes two general ubsan issues in ext-dce, both related

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

https://gcc.gnu.org/g:2c215f2b3022907b79a4a5caa855ee5f88f129e5 commit 2c215f2b3022907b79a4a5caa855ee5f88f129e5 Author: Pan Li Date: Sat Aug 17 19:27:11 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

https://gcc.gnu.org/g:22f0e0f7d321251423a640c5f2b82987917b6d81 commit 22f0e0f7d321251423a640c5f2b82987917b6d81 Author: Pan Li Date: Fri Aug 9 10:26:32 2024 +0800 RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278] For QI/HImode of .SAT_ADD, the operan

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

https://gcc.gnu.org/g:370eaa82697d65d92d5a6270978e18b777bdcfbe commit 370eaa82697d65d92d5a6270978e18b777bdcfbe Author: Pan Li Date: Sat Aug 17 18:04:00 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Avoid right shifting signed value on ext-dce.cc

https://gcc.gnu.org/g:821e603d560221ec4ab517ce1eb1b0152d9c1eac commit 821e603d560221ec4ab517ce1eb1b0152d9c1eac Author: Jeff Law Date: Sat Aug 17 15:10:38 2024 -0600 [committed] Avoid right shifting signed value on ext-dce.cc This is analogous to a prior patch to ext-dce which fixe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

https://gcc.gnu.org/g:c59b5f7b505aae5c1d342a309b6603db2a7c9f19 commit c59b5f7b505aae5c1d342a309b6603db2a7c9f19 Author: Kevin Kirspel Date: Sat Aug 17 14:37:18 2024 -0600 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V The attach patch is specific to the RTEMS RI

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

https://gcc.gnu.org/g:310cb65e2e93e90d5258c60733e1b70f0c8a7e88 commit 310cb65e2e93e90d5258c60733e1b70f0c8a7e88 Author: Jin Ma Date: Sat Aug 17 10:18:03 2024 -0600 RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics When rs1 is the immediate 0, the following ICE

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116282] Stabilize pattern conditions

https://gcc.gnu.org/g:36ad5c69a273cb36accd27e70423c81cbd7fbcf9 commit 36ad5c69a273cb36accd27e70423c81cbd7fbcf9 Author: Jeff Law Date: Sat Aug 17 09:52:55 2024 -0600 [RISC-V][PR target/116282] Stabilize pattern conditions So as expected the core problem with target/116282 is that t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker

https://gcc.gnu.org/g:5b2f688a7fad7b06e4f4fa070373e2781f8b4494 commit 5b2f688a7fad7b06e4f4fa070373e2781f8b4494 Author: Jin Ma Date: Sat Aug 17 09:29:11 2024 -0600 RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker When compiling an interface for rounding of type 'vf

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix incorrect operand for vwsll auto-vect

https://gcc.gnu.org/g:457adc650d8fdaf6bc153930bf60038189d7 commit 457adc650d8fdaf6bc153930bf60038189d7 Author: Pan Li Date: Sat Aug 17 09:25:58 2024 -0600 RISC-V: Bugfix incorrect operand for vwsll auto-vect This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add auto-vect pattern for vector rotate shift

https://gcc.gnu.org/g:ed5cb5a783e2d7aab117bf575e45089a86d4e3c4 commit ed5cb5a783e2d7aab117bf575e45089a86d4e3c4 Author: Feng Wang Date: Sat Aug 17 08:40:42 2024 -0600 RISC-V: Add auto-vect pattern for vector rotate shift This patch add the vector rotate shift pattern for auto-vect.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

https://gcc.gnu.org/g:168bc423824158a6933c06b1ac8a03dbf1736ac6 commit 168bc423824158a6933c06b1ac8a03dbf1736ac6 Author: 曾治金 Date: Wed Aug 14 14:06:23 2024 +0800 RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305] This patch is to fix the bug (BugId:116305) introduced by

[gcc r15-2989] [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc

https://gcc.gnu.org/g:f10d2ee95356b9de6c44d701c4dfa8fb088714d2 commit r15-2989-gf10d2ee95356b9de6c44d701c4dfa8fb088714d2 Author: Jeff Law Date: Sun Aug 18 16:55:52 2024 -0600 [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc This fixes two general ubsan issues in ext-dce, bot

[gcc r15-2975] [committed] Avoid right shifting signed value on ext-dce.cc

https://gcc.gnu.org/g:61e179b1b363454926504fac13b554ad7f1b0f72 commit r15-2975-g61e179b1b363454926504fac13b554ad7f1b0f72 Author: Jeff Law Date: Sat Aug 17 15:10:38 2024 -0600 [committed] Avoid right shifting signed value on ext-dce.cc This is analogous to a prior patch to ext-dce

[gcc r15-2974] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

https://gcc.gnu.org/g:efcfd1d2ad8779b5c1b41b7f702516ca1da46925 commit r15-2974-gefcfd1d2ad8779b5c1b41b7f702516ca1da46925 Author: Kevin Kirspel Date: Sat Aug 17 14:37:18 2024 -0600 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V The attach patch is specific to th

[gcc r15-2973] Adjust v850 rotate expander to allow more cases for V850E3V5

https://gcc.gnu.org/g:abfc140579682598cd178eb9d0b0160bbfafc633 commit r15-2973-gabfc140579682598cd178eb9d0b0160bbfafc633 Author: Jeff Law Date: Sat Aug 17 10:30:48 2024 -0600 Adjust v850 rotate expander to allow more cases for V850E3V5 The recent if-conversion changes tripped a fa

[gcc r15-2972] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

https://gcc.gnu.org/g:6d734ba485547329599f12bea63842a4fba8d72c commit r15-2972-g6d734ba485547329599f12bea63842a4fba8d72c Author: Jin Ma Date: Sat Aug 17 10:18:03 2024 -0600 RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics When rs1 is the immediate 0, the fol

[gcc r15-2971] [RISC-V][PR target/116282] Stabilize pattern conditions

https://gcc.gnu.org/g:7aed8dedeb9613925930447bf2457c3fd9972d91 commit r15-2971-g7aed8dedeb9613925930447bf2457c3fd9972d91 Author: Jeff Law Date: Sat Aug 17 09:52:55 2024 -0600 [RISC-V][PR target/116282] Stabilize pattern conditions So as expected the core problem with target/116282

[gcc r15-2970] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker

https://gcc.gnu.org/g:3f51684ac05f065a87c53d9506400cbe97af6b79 commit r15-2970-g3f51684ac05f065a87c53d9506400cbe97af6b79 Author: Jin Ma Date: Sat Aug 17 09:29:11 2024 -0600 RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker When compiling an interface for rounding o

[gcc r15-2969] RISC-V: Bugfix incorrect operand for vwsll auto-vect

https://gcc.gnu.org/g:06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1 commit r15-2969-g06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1 Author: Pan Li Date: Sat Aug 17 09:25:58 2024 -0600 RISC-V: Bugfix incorrect operand for vwsll auto-vect This patch would like to fix one ICE when rv64gcv_zvbb

[gcc r15-2968] RISC-V: Add auto-vect pattern for vector rotate shift

https://gcc.gnu.org/g:54b228d80c54d32ab49cee6148cfd1364b2bc817 commit r15-2968-g54b228d80c54d32ab49cee6148cfd1364b2bc817 Author: Feng Wang Date: Sat Aug 17 08:40:42 2024 -0600 RISC-V: Add auto-vect pattern for vector rotate shift This patch add the vector rotate shift pattern for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Drop accidental hunk.

https://gcc.gnu.org/g:0a279dfd56e5e38bf3c23257b92bab1ccfcd0747 commit 0a279dfd56e5e38bf3c23257b92bab1ccfcd0747 Author: Jeff Law Date: Fri Aug 16 13:52:44 2024 -0600 Drop accidental hunk. Not worth the effort to find the patch where it got incorrectly introduced (duplicate). D

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Manual applicatoin of riscv specific changes from:

https://gcc.gnu.org/g:e6b322cc9a99caf4805952efc3ee1a4a6d0f8988 commit e6b322cc9a99caf4805952efc3ee1a4a6d0f8988 Author: Jeff Law Date: Fri Aug 16 13:27:37 2024 -0600 Manual applicatoin of riscv specific changes from: commit acc70606c59e3f14072cc8a164362e728d8df5d6 Author: Sam J

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Manual application of riscv specific changes from:

https://gcc.gnu.org/g:0c66fc473a560e3cf87b07568044aec60dfad0a4 commit 0c66fc473a560e3cf87b07568044aec60dfad0a4 Author: Jeff Law Date: Fri Aug 16 13:24:27 2024 -0600 Manual application of riscv specific changes from: commit 2e662dedf84aa23fdff7bceca040432bf9f1ab72 Author: Sam J

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix missing abi arg in test

https://gcc.gnu.org/g:48816efb27d1ed055eebc41fac543d183784f85e commit 48816efb27d1ed055eebc41fac543d183784f85e Author: Edwin Lu Date: Wed Aug 7 10:34:10 2024 -0700 RISC-V: Fix missing abi arg in test The following test was failing when building on 32 bit targets due to not ove

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] testsuite: fix dg-add-options vs. dg-options ordering

https://gcc.gnu.org/g:d9c50df2fcbf50b078a31c0d876a68b25b0f4d4a commit d9c50df2fcbf50b078a31c0d876a68b25b0f4d4a Author: Sam James Date: Sat Jul 27 00:31:54 2024 +0100 testsuite: fix dg-add-options vs. dg-options ordering Per gccint, dg-add-options must be placed after all dg-option

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Restrict pr116202-run-1.c test to riscv_v target

https://gcc.gnu.org/g:aa312daf3cf0333d369f9a9abaf5b356881cad0e commit aa312daf3cf0333d369f9a9abaf5b356881cad0e Author: Mark Wielaard Date: Mon Aug 12 22:25:42 2024 +0200 Restrict pr116202-run-1.c test to riscv_v target The testcase uses -march=rv64gcv and dg-do run, so should be

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial: Just the testsuite bits...

https://gcc.gnu.org/g:84684236ca332f9d4732c9d6c8a892ea058d61a1 commit 84684236ca332f9d4732c9d6c8a892ea058d61a1 Author: Pan Li Date: Tue Aug 6 20:59:37 2024 +0800 Partial: Just the testsuite bits... Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins

https://gcc.gnu.org/g:7192fa62bb919ca72168af1c31a95ebb6cbcfff6 commit 7192fa62bb919ca72168af1c31a95ebb6cbcfff6 Author: Vineet Gupta Date: Thu Aug 15 09:24:27 2024 -0700 RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins Currently these builtins use float co

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] genoutput: Accelerate the place_operands function.

https://gcc.gnu.org/g:5433bd714737a9b18b54f3579806af2c1f98656d commit 5433bd714737a9b18b54f3579806af2c1f98656d Author: Xianmiao Qu Date: Wed May 22 15:25:16 2024 +0800 genoutput: Accelerate the place_operands function. With the increase in the number of modes and patterns for some

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix non-obvious comment typos

https://gcc.gnu.org/g:983da7ad96ff0920ceb3c439a29fdbcf4512fbae commit 983da7ad96ff0920ceb3c439a29fdbcf4512fbae Author: Patrick O'Neill Date: Mon Aug 5 15:29:33 2024 -0700 RISC-V: Fix non-obvious comment typos This fixes the remainder of the typos I found when reading various parts

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116283] Fix split code for recent Zbs improvements with masked bit positions

https://gcc.gnu.org/g:d0d826c509e0cccadba399eaa57f8d63a51178c5 commit d0d826c509e0cccadba399eaa57f8d63a51178c5 Author: Jeff Law Date: Fri Aug 9 17:46:01 2024 -0600 [RISC-V][PR target/116283] Fix split code for recent Zbs improvements with masked bit positions So Patrick's fuzzer

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable stack clash in alloca

https://gcc.gnu.org/g:8eced564ddf62282cd2737a7b3487088fc32eff4 commit 8eced564ddf62282cd2737a7b3487088fc32eff4 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:27 2024 -0300 RISC-V: Enable stack clash in alloca Add the TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE to riscv

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support to vector stack-clash protection

https://gcc.gnu.org/g:9673f136d09980bbc7be4e3e82fec1ef37652ea0 commit 9673f136d09980bbc7be4e3e82fec1ef37652ea0 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:23 2024 -0300 RISC-V: Add support to vector stack-clash protection Adds basic support to vector stack-clash protecti

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Stack-clash protection implemention

https://gcc.gnu.org/g:7f6b6a5710258a720d2d35d14c30877b729b4833 commit 7f6b6a5710258a720d2d35d14c30877b729b4833 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:20 2024 -0300 RISC-V: Stack-clash protection implemention This implements stack-clash protection for riscv, with

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move riscv_v_adjust_scalable_frame

https://gcc.gnu.org/g:fec211cf435acc4f3ebc32c59314c2816291ea96 commit fec211cf435acc4f3ebc32c59314c2816291ea96 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:17 2024 -0300 RISC-V: Move riscv_v_adjust_scalable_frame Move riscv_v_adjust_scalable_frame () in preparation for th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Small stack tie changes

https://gcc.gnu.org/g:49000f578de1ac20872083e19f709cf41b4a81a7 commit 49000f578de1ac20872083e19f709cf41b4a81a7 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:12 2024 -0300 RISC-V: Small stack tie changes Enable the register used by riscv_emit_stack_tie () to be passed as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx

https://gcc.gnu.org/g:a9e84ce68bf3779e5bbc643cfab457803f7b5ad7 commit a9e84ce68bf3779e5bbc643cfab457803f7b5ad7 Author: Christoph Müllner Date: Tue Aug 6 06:48:59 2024 +0200 RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx When enabling XTheadFmv/Zfa and XThead(F)MemIdx,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: xthead(f)memidx: Eliminate optimization patterns

https://gcc.gnu.org/g:c2fbe69dbc0c7ef43ad3d99122f0998be89fcb33 commit c2fbe69dbc0c7ef43ad3d99122f0998be89fcb33 Author: Christoph Müllner Date: Tue Jul 30 13:10:59 2024 +0200 RISC-V: xthead(f)memidx: Eliminate optimization patterns We have a huge amount of optimization patterns (in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test

https://gcc.gnu.org/g:fef123664d31ed2ccb29693a8345a72e209da6c4 commit fef123664d31ed2ccb29693a8345a72e209da6c4 Author: Christoph Müllner Date: Tue Aug 6 07:24:07 2024 +0200 RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test Test file xtheadfmemidx-medany.c has

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'

https://gcc.gnu.org/g:05611fbd80acad68fca9ce7f951977699b27d20b commit 05611fbd80acad68fca9ce7f951977699b27d20b Author: Jin Ma Date: Thu Aug 8 07:49:51 2024 -0600 RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' gcc/ChangeLog: * config/riscv/riscv.h (RISCV_DWAR

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments

https://gcc.gnu.org/g:616f63ee647e61d3cfb25ecf68c50ecbef364828 commit 616f63ee647e61d3cfb25ecf68c50ecbef364828 Author: Jeff Law Date: Thu Aug 8 07:42:26 2024 -0600 [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments This was supposed to go out the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Rearrange SLP nodes with duplicate statements [PR98138]

https://gcc.gnu.org/g:184712c1c6bd5d46c37bba76996e1f3f6b343389 commit 184712c1c6bd5d46c37bba76996e1f3f6b343389 Author: Manolis Tsamis Date: Tue Jun 25 08:00:04 2024 -0700 Rearrange SLP nodes with duplicate statements [PR98138] This change checks when a two_operators SLP node has m

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix Wstringop-overflow-47.c warning in RISC-V target.

https://gcc.gnu.org/g:d18d1a744832cb6deda2271c6ea9ce39d7b7f672 commit d18d1a744832cb6deda2271c6ea9ce39d7b7f672 Author: Jiawei Date: Tue Jul 16 08:06:25 2024 +0800 Fix Wstringop-overflow-47.c warning in RISC-V target. Update warning test info for RISC-V target, compared on godbolt:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Minimal support for Zimop extension.

https://gcc.gnu.org/g:16a39f8b7f4192ddeff4efd2b9131adb6352b071 commit 16a39f8b7f4192ddeff4efd2b9131adb6352b071 Author: Jiawei Date: Fri Aug 2 23:23:14 2024 +0800 RISC-V: Minimal support for Zimop extension. This patch support Zimop and Zcmop extension[1].To enable GCC to recognize

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Update .SAT_TRUNC dump check due to middle-end change

https://gcc.gnu.org/g:7982b3fb96a0187466024f4ae22f5eb60106b2ee commit 7982b3fb96a0187466024f4ae22f5eb60106b2ee Author: Pan Li Date: Mon Aug 5 16:01:11 2024 +0800 RISC-V: Update .SAT_TRUNC dump check due to middle-end change Due to recent middle-end change, update the .SAT_TRUNC ex

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code

https://gcc.gnu.org/g:f8512afeda441a4469002db034bbe6dfaf25a5ce commit f8512afeda441a4469002db034bbe6dfaf25a5ce Author: Patrick O'Neill Date: Mon Aug 5 14:19:58 2024 -0700 RISC-V: Fix typos in code This fixes typos in function names and executed code. gcc/ChangeLog:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix comment typos

https://gcc.gnu.org/g:69ce456669e1f1549705197cca46e4fd47f509fa commit 69ce456669e1f1549705197cca46e4fd47f509fa Author: Patrick O'Neill Date: Mon Aug 5 14:13:12 2024 -0700 RISC-V: Fix comment typos This fixes most of the typos I found when reading various parts of the RISC-V b

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix format-diag warning from improperly formatted url

https://gcc.gnu.org/g:a20c435f8158401e56339bbdfe4c2b5d60ebed96 commit a20c435f8158401e56339bbdfe4c2b5d60ebed96 Author: Patrick O'Neill Date: Tue Aug 6 08:16:26 2024 -0700 RISC-V: Fix format-diag warning from improperly formatted url gcc/ChangeLog: PR target/116152

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add deprecation warning to LP64E abi

https://gcc.gnu.org/g:6c244049d986b95658006b265b79ac014b325cbc commit 6c244049d986b95658006b265b79ac014b325cbc Author: Patrick O'Neill Date: Tue Jul 30 17:32:09 2024 -0700 RISC-V: Add deprecation warning to LP64E abi gcc/ChangeLog: PR target/116152 * c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reject 'd' extension with ILP32E ABI

https://gcc.gnu.org/g:5e106d5552f11a16a83f8e48852dc3803b010c11 commit 5e106d5552f11a16a83f8e48852dc3803b010c11 Author: Patrick O'Neill Date: Tue Jul 30 14:28:23 2024 -0700 RISC-V: Reject 'd' extension with ILP32E ABI Also add a testcase for -mabi=lp64d where 'd' is required.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.

https://gcc.gnu.org/g:b9820a4a0d683a9b57ab72f7f4e60deb0976513e commit b9820a4a0d683a9b57ab72f7f4e60deb0976513e Author: Jiawei Date: Mon Aug 5 20:15:59 2024 +0800 testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50,51. The test has been observed to pass on

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Improve length attributes for atomic insn sequences

https://gcc.gnu.org/g:11967b054b91d58e8555886664ae91603032c14d commit 11967b054b91d58e8555886664ae91603032c14d Author: Patrick O'Neill Date: Thu Aug 1 20:27:52 2024 -0700 RISC-V: Improve length attributes for atomic insn sequences gcc/ChangeLog: * config/riscv/syn

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].

https://gcc.gnu.org/g:b870cb81038f703c970ce4eb7c70991f544405b0 commit b870cb81038f703c970ce4eb7c70991f544405b0 Author: Robin Dapp Date: Wed Jul 31 16:54:03 2024 +0200 RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149]. In PR116149 we choose a wrong vector length

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: NFC: Do not use zicond for pr105314 testcases

https://gcc.gnu.org/g:b6a1ecda25fc90724585f94eb618e7578722ea83 commit b6a1ecda25fc90724585f94eb618e7578722ea83 Author: Xiao Zeng Date: Thu Jul 25 09:50:03 2024 +0800 RISC-V: NFC: Do not use zicond for pr105314 testcases gcc/testsuite/ChangeLog: * gcc.target/riscv/

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/116104] Fix more rtl-checking failures in ext-dce

https://gcc.gnu.org/g:9bdf6995bf4069c2e317b0490c9afa6302e8a037 commit 9bdf6995bf4069c2e317b0490c9afa6302e8a037 Author: Jeff Law Date: Wed Jul 31 11:30:27 2024 -0600 [target/116104] Fix more rtl-checking failures in ext-dce More enable-rtl-checking fixes for ext-dce. Very similar

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug

https://gcc.gnu.org/g:0476f5316e781a1ea0d7ef91ed654358f4bccd80 commit 0476f5316e781a1ea0d7ef91ed654358f4bccd80 Author: Jeff Law Date: Wed Jul 31 10:15:01 2024 -0600 [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug This fixes a testsuite regression seen

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add configure check for B extention support

https://gcc.gnu.org/g:463bd569ca686a364c0c3442b623759353d84d2f commit 463bd569ca686a364c0c3442b623759353d84d2f Author: Edwin Lu Date: Wed Jul 24 16:37:18 2024 -0700 RISC-V: Add configure check for B extention support Binutils 2.42 and before don't recognize the b extension in the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add basic support for the Zacas extension

https://gcc.gnu.org/g:cbaa7b2663e48ec9fafcad634a8e06c2aa1a32d0 commit cbaa7b2663e48ec9fafcad634a8e06c2aa1a32d0 Author: Gianluca Guida Date: Mon Jul 29 15:13:46 2024 -0700 RISC-V: Add basic support for the Zacas extension This patch adds support for amocas.{b|h|w|d}. Support for am

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove configure check for zabha

https://gcc.gnu.org/g:b2df229aa9c1b5a9fb77c23456903cf911c5f838 commit b2df229aa9c1b5a9fb77c23456903cf911c5f838 Author: Patrick O'Neill Date: Mon Jul 29 19:52:02 2024 -0700 RISC-V: Remove configure check for zabha This patch removes the zabha configure check since it's not a breaki

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Take Xmode instead of Pmode for ussub expanding

https://gcc.gnu.org/g:6bf3d45cb3d7f54412fd17b7f9452e7ec52d7adf commit 6bf3d45cb3d7f54412fd17b7f9452e7ec52d7adf Author: Pan Li Date: Tue Jul 30 13:56:40 2024 +0800 RISC-V: Take Xmode instead of Pmode for ussub expanding The Pmode is designed for pointer, thus leverage the Xmode in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/116104] Fix test guarding UINTVAL to extract shift count

https://gcc.gnu.org/g:6ca3dabccff3d3cb8ea1a67be38373eebca521c4 commit 6ca3dabccff3d3cb8ea1a67be38373eebca521c4 Author: Jeff Law Date: Mon Jul 29 16:17:25 2024 -0600 [target/116104] Fix test guarding UINTVAL to extract shift count Minor oversight in the ext-dce bits. If the shift

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][target/116085] Fix rv64 minmax extension avoidance splitter

https://gcc.gnu.org/g:ed6d11c16d69b1cf388bfa6dbc00fa3b34ade969 commit ed6d11c16d69b1cf388bfa6dbc00fa3b34ade969 Author: Jeff Law Date: Fri Jul 26 17:30:08 2024 -0600 [RISC-V][target/116085] Fix rv64 minmax extension avoidance splitter A patch introduced a pattern to avoid unnecessa

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Work around bare apostrophe in error string.

https://gcc.gnu.org/g:37cbd2160d01bea81623f1ca506b731ac0f36bbd commit 37cbd2160d01bea81623f1ca506b731ac0f36bbd Author: Robin Dapp Date: Fri Jul 26 12:58:38 2024 +0200 RISC-V: Work around bare apostrophe in error string. An unquoted apostrophe slipped through when testing the recen

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116039] Fix life computation for promoted subregs

https://gcc.gnu.org/g:7d226394382ff284f8c24cbbf6a677023b72111d commit 7d226394382ff284f8c24cbbf6a677023b72111d Author: Jeff Law Date: Thu Jul 25 12:32:28 2024 -0600 [PR rtl-optimization/116039] Fix life computation for promoted subregs So this turned out to be a neat little test a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Trivial testcase adjustment

https://gcc.gnu.org/g:16d1997090340cd587c85450983bf545245dc5bf commit 16d1997090340cd587c85450983bf545245dc5bf Author: Jeff Law Date: Thu Jul 25 08:42:04 2024 -0600 [committed] Trivial testcase adjustment I made pr116037.c dependent on int32 just based on the constants used witho

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:13370bdcaf62a62b59845f9c07c942df7c3a8bd3 commit 13370bdcaf62a62b59845f9c07c942df7c3a8bd3 Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we use a mul

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

https://gcc.gnu.org/g:78e0cd7d2e7f3a09d3ce08a407d91d16e9877246 commit 78e0cd7d2e7f3a09d3ce08a407d91d16e9877246 Author: Juzhe-Zhong Date: Thu Feb 1 23:45:50 2024 +0800 RISC-V: Allow LICM hoist POLY_INT configuration code sequence Realize in recent benchmark evaluation (coremark-pro

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce

https://gcc.gnu.org/g:ecbda5a53e691ce963e82aff354f1a43df30d762 commit ecbda5a53e691ce963e82aff354f1a43df30d762 Author: Jeff Law Date: Wed Jul 24 11:16:26 2024 -0600 [rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce So this has been in the hopper s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877][6/n] Add testcase from pr115877

https://gcc.gnu.org/g:b95ba68bf28a28ec50c3fa96b1587cc9a97af4b9 commit b95ba68bf28a28ec50c3fa96b1587cc9a97af4b9 Author: Jeff Law Date: Tue Jul 23 19:11:04 2024 -0600 [PR rtl-optimization/115877][6/n] Add testcase from pr115877 This just adds the testcase from pr115877. It's workin

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