https://gcc.gnu.org/g:9cefcbbe66343a37b89353aa9c23cd289bf01777
commit 9cefcbbe66343a37b89353aa9c23cd289bf01777 Author: Michael Meissner <meiss...@linux.ibm.com> Date: Tue May 14 21:19:38 2024 -0400 Update to tar branch. 2024-05-14 Michael Meissner <meiss...@linux.ibm.com> * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove -mtar support from -mcpu=power8. (OTHER_POWER10_MASKS): Add -mtar, -mmfspr, and -mintspr. (POWERPC_MASKS): Add -mintspr. * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr. (rs6000_option_override_internal): Do not allow -mtar unless power9 or power10. (rs6000_opt_masks): Add -mmfspr and -minttar. * config/rs6000/rs6000.opt (-mintspr): New switch. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 14 +++++++++----- gcc/config/rs6000/rs6000.cc | 26 +++++++++++++++++--------- gcc/config/rs6000/rs6000.opt | 4 ++++ 3 files changed, 30 insertions(+), 14 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index f53bd3e7dcba..a526918927ff 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -51,17 +51,17 @@ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ - | OPTION_MASK_MFSPR \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC \ - | OPTION_MASK_TAR) + | OPTION_MASK_QUAD_MEMORY_ATOMIC) /* ISA masks setting fusion options. */ #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ | OPTION_MASK_P8_FUSION_SIGN) /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add - FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ + FLOAT128_HW here until we are ready to make -mfloat128 on by default. While + ISA 2.07 (power9) supports the TAR register, don't enable it here, because + it doesn't seem to help. */ #define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ @@ -80,9 +80,12 @@ /* We comment out PCREL_OPT here to disable it by default because SPEC2017 performance was degraded by it. */ #define OTHER_POWER10_MASKS (OPTION_MASK_MMA \ + | OPTION_MASK_INTSPR \ + | OPTION_MASK_MFSPR \ | OPTION_MASK_PCREL \ /* | OPTION_MASK_PCREL_OPT */ \ - | OPTION_MASK_PREFIXED) + | OPTION_MASK_PREFIXED \ + | OPTION_MASK_TAR) #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ @@ -135,6 +138,7 @@ | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ + | OPTION_MASK_INTSPR \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MFSPR \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 9f9f942a7860..7f4ee65c42c4 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1930,11 +1930,8 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if (CR_REGNO_P (regno)) return GET_MODE_CLASS (mode) == MODE_CC; - if (CA_REGNO_P (regno)) - return mode == Pmode || mode == SImode; - - /* Limit SPR registers to integer modes that can fit in a single register. - Do not allow complex modes. */ + /* If desired, limit SPR registers to integer modes that can fit in a single + register. Do not allow complex modes. */ switch (regno) { case LR_REGNO: @@ -1942,10 +1939,10 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) case TAR_REGNO: case VRSAVE_REGNO: case VSCR_REGNO: - return (orig_mode == Pmode - || orig_mode == SImode - || orig_mode == HImode - || orig_mode == QImode); + case CA_REGNO: + return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (Pmode) + && !COMPLEX_MODE_P (orig_mode) + && (!TARGET_INTSPR || SCALAR_INT_MODE_P (mode))); default: break; @@ -4221,6 +4218,15 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW; } + /* If -mtar, make sure we have at least a power9. */ + if (TARGET_TAR && !TARGET_P9_MISC) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_TAR) != 0) + error ("%qs requires %qs", "-mtar", "-mcpu=power9"); + + rs6000_isa_flags &= ~OPTION_MASK_TAR; + } + /* Enable -mprefixed by default on power10 systems. */ if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED) == 0) rs6000_isa_flags |= OPTION_MASK_PREFIXED; @@ -24519,9 +24525,11 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power11", OPTION_MASK_POWER11, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, + { "intspr", OPTION_MASK_INTSPR, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, { "mfcrf", OPTION_MASK_MFCRF, false, true }, { "mfpgpr", 0, false, true }, + { "mfspr", OPTION_MASK_MFSPR, false, true }, { "mma", OPTION_MASK_MMA, false, true }, { "modulo", OPTION_MASK_MODULO, false, true }, { "mulhw", OPTION_MASK_MULHW, false, true }, diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 8b21865f9831..9e9efa60bea5 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -615,6 +615,10 @@ mmfspr Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags) Generate (do not generate) code making move from SPR register expensive. +mintspr +Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags) +Require (disallow) SPR registers to hold only integer modes and not floating point modes. + mrelative-jumptables Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save