https://gcc.gnu.org/g:795021d9bc8546ccc51bacc899b6077c6928067b

commit r15-2347-g795021d9bc8546ccc51bacc899b6077c6928067b
Author: Andrew Pinski <quic_apin...@quicinc.com>
Date:   Mon Jul 22 15:39:37 2024 -0700

    aarch64: sve: Rename aarch64_bic to standard pattern, andn
    
    Now there is an optab for bic, andn since r15-1890-gf379596e0ba99d.
    This moves aarch64_bic for sve over to use it instead.
    
    Note unlike the simd bic patterns, the operands were already
    in the order that was expected for the optab so no swapping
    was needed.
    
    Built and tested on aarch64-linux-gnu with no regressions.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-sve-builtins-base.cc (svbic_impl::expand): 
Update
            to use andn optab instead of using code_for_aarch64_bic.
            * config/aarch64/aarch64-sve.md (@aarch64_bic<mode>): Rename to ...
            (andn<mode>3): This.
    
    Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com>

Diff:
---
 gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +-
 gcc/config/aarch64/aarch64-sve.md               | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index aa26370d397f..a2268353ae31 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -271,7 +271,7 @@ public:
       }
 
     if (e.pred == PRED_x)
-      return e.use_unpred_insn (code_for_aarch64_bic (e.vector_mode (0)));
+      return e.use_unpred_insn (e.direct_optab_handler (andn_optab));
 
     return e.use_cond_insn (code_for_cond_bic (e.vector_mode (0)));
   }
diff --git a/gcc/config/aarch64/aarch64-sve.md 
b/gcc/config/aarch64/aarch64-sve.md
index 5331e7121d55..c3ed5075c4ed 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4641,8 +4641,8 @@
 ;; - BIC
 ;; -------------------------------------------------------------------------
 
-;; Unpredicated BIC.
-(define_expand "@aarch64_bic<mode>"
+;; Unpredicated BIC; andn named pattern.
+(define_expand "andn<mode>3"
   [(set (match_operand:SVE_I 0 "register_operand")
        (and:SVE_I
          (unspec:SVE_I

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