Re: [PATCH] Implement -fsanitize=float-cast-overflow

On Thu, May 15, 2014 at 09:29:44PM +, Joseph S. Myers wrote: > On Thu, 15 May 2014, Jakub Jelinek wrote: > > > But I think we can't use decimal_real_from_string, we'd need a variant > > of that function that would allow specification of the rounding mode > > My point is that you can use "%.*RUe

Re: [PATCH] Make SCCVN constant-fold calls

On Thu, 15 May 2014, Richard Biener wrote: > > For some odd reason I didn't implement this earlier. This is one > major source of 2nd-stage opportunities that come up when running > two adjacent FRE passes. > > Bootstrap and regtest ongoing on x86_64-unknown-linux-gnu. The following is what I

Re: patch8.diff updated Was: Re: GCC's -fsplit-stack disturbing Mach's vm_allocate

On Wed, 2014-05-07 at 10:18 +0200, Svante Signell wrote: > On Tue, 2014-05-06 at 15:26 +0200, Samuel Thibault wrote: Attached is an updated patch8.diff. Arch specific code to src/libgo/mksysinfo.sh has been added, now other systems are not affected by the patch except the SYS_FCNTL part. For that

Re: [PATCH][1/n][RFC] Make FRE/PRE somewhat predicate aware

On Thu, 8 May 2014, Richard Biener wrote: > > Ok, not really predicate aware, but this makes value-numbering > pessimistically handle non-executable edges. In the following > patch groundwork is laid and PHI value-numbering is adjusted > to take advantage of edges known to be not executable. >

Re: [AArch64 costs 0/18] Improve address- and rtx-cost models

This series is OK. /Marcus On 27 March 2014 17:33, James Greenhalgh wrote: > Hi, > > This patch series improves the costing model in the AArch64 backend to > match a number of new idioms. > > This patch is a combination of a series I had been working on, with the > cost-model for XGene-1 proposed

[AArch64 costs] Fixup to costing of FNMUL

Hi, While waiting for approval of the costs patches, I spotted this bug. FNMUL should be costed like an FMUL, rather than being costed like an FMA instruction. Bootstrapped and tested in series with the costs patches with no issues. I see Marcus has approved the patch series, so is this OK to g

Re: RFA: Fix calculation of size of builtin setjmp buffer

Hi Eric, OK - here is your version of the patch, extended with a comment which I think is helpful for other people reading the code, and with the changes to builtins.c and md.texi removed, since the size of the buffer is not changing. Is this version OK to apply ? Cheers Nick gcc/Cha

Re: [AArch64 costs] Fixup to costing of FNMUL

On 16 May 2014 09:26, James Greenhalgh wrote: > 2014-05-15 James Greenhalgh > > * config/aarch64/aarch64.c (aarch64_rtx_mult_cost): Fix FNMUL case. OK /Marcus

Avoiding some garbage rtl from instantiate_virtual_regs

It seems that in a typical -O0 compile the amount of rtl that starts out as needed but becomes garbage is only slightly less than half of the total amount created. One of the big offenders is the vregs pass, which creates new PLUSes when instanstiating a virtual register + a constant and which cre

[PATCH SH] Don't switch mode around fmov (pr61195)

Hi, This patch reduces the number of unnecessary PR mode switches for single precision moves. When FPSCR.SZ is not forced. Test illustration in the patch Regtested for sh-none-elf with -m4, (-m2a still running), bootstrapped on sh4-linux-elf board. ok for trunk ? Many thanks, Christian

RE: [PATCH, AArch64] Use MOVN to generate 64-bit negative immediates where sensible

Ping. This should be relatively simple to review. Many thanks. > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Ian Bolton > Sent: 08 May 2014 18:36 > To: gcc-patches > Subject: [PATCH, AArch64] Use MOVN to generate 64-bit

RE: [PATCH, AArch64] Fix macro in vdup_lane_2 test case

Ping. This may well be classed as "obvious", but that's not obvious to me, so I request a review. Many thanks. > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Ian Bolton > Sent: 08 May 2014 18:42 > To: gcc-patches > Subjec

Re: [Patch, avr] Propagate -mrelax gcc driver flag to assembler

Am 05/15/2014 09:55 AM, schrieb Senthil Kumar Selvaraj: On Wed, May 14, 2014 at 12:56:54PM +0200, Rainer Orth wrote: Georg-Johann Lay writes: Or what about simply that, which works for me: Index: config/avr/avr.h === --- config

RE: [PATCH] Fix PR54733 Optimize endian independent load/store

Ping? Best regards, Thomas Preud'homme > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Friday, May 09, 2014 6:26 PM > To: GCC Patches > Subject: RE: [PATCH] Fix PR54733 Optimize endian independen

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Fri, May 16, 2014 at 12:57 AM, Steven Bosscher wrote: > On Thu, May 15, 2014 at 9:26 AM, bin.cheng wrote: >> Hi, >> Targets like ARM and AARCH64 support double-word load store instructions, >> and these instructions are generally faster than the corresponding two >> load/stores. GCC currently

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Fri, May 16, 2014 at 1:13 AM, Jeff Law wrote: > On 05/15/14 10:51, Mike Stump wrote: >> >> On May 15, 2014, at 12:26 AM, bin.cheng wrote: >>> >>> Here comes up with a new GCC pass looking through each basic block >>> and merging paired load store even they are not adjacent to each >>> other. >

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Fri, May 16, 2014 at 12:51 AM, Mike Stump wrote: > On May 15, 2014, at 12:26 AM, bin.cheng wrote: >> Here comes up with a new GCC pass looking through each basic block and >> merging paired load store even they are not adjacent to each other. > > So I have a target that has load and store mult

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Thu, May 15, 2014 at 6:31 PM, Oleg Endo wrote: > Hi, > > On 15 May 2014, at 09:26, "bin.cheng" wrote: > >> Hi, >> Targets like ARM and AARCH64 support double-word load store instructions, >> and these instructions are generally faster than the corresponding two >> load/stores. GCC currently u

Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.

On Fri, Mar 28, 2014 at 03:39:53PM +, James Greenhalgh wrote: > On Fri, Mar 28, 2014 at 03:09:22PM +, pins...@gmail.com wrote: > > > On Mar 28, 2014, at 7:48 AM, James Greenhalgh > > > wrote: > > > On Fri, Mar 28, 2014 at 11:11:58AM +, pins...@gmail.com wrote: > > >>> On Mar 28, 2014,

Re: [PATCH] Fix PR54733 Optimize endian independent load/store

On Fri, May 16, 2014 at 12:07 PM, Thomas Preud'homme wrote: > Ping? Sorry ... > Best regards, > > Thomas Preud'homme > >> -Original Message- >> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- >> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme >> Sent: Friday, May 09, 2014 6:2

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Fri, May 16, 2014 at 12:10 PM, Bin.Cheng wrote: > On Thu, May 15, 2014 at 6:31 PM, Oleg Endo wrote: >> Hi, >> >> On 15 May 2014, at 09:26, "bin.cheng" wrote: >> >>> Hi, >>> Targets like ARM and AARCH64 support double-word load store instructions, >>> and these instructions are generally faste

Re: [PATCH] Fix PR54733 Optimize endian independent load/store

> On May 16, 2014, at 3:48 AM, Richard Biener > wrote: > > On Fri, May 16, 2014 at 12:07 PM, Thomas Preud'homme > wrote: >> Ping? > > Sorry ... > >> Best regards, >> >> Thomas Preud'homme >> >>> -Original Message- >>> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- >>> ow

Re: add dbgcnt and opt-info support for devirtualization

On Fri, May 16, 2014 at 1:54 AM, Xinliang David Li wrote: > Hi, debugging runtime bugs due to devirtualization can be hard for > very large C++ programs with complicated class hierarchy. This patch > adds the support to report this high level transformation via > -fopt-info (not hidden inside dump

Re: [PATCH] Fix PR54733 Optimize endian independent load/store

On Fri, May 16, 2014 at 12:56 PM, wrote: > > >> On May 16, 2014, at 3:48 AM, Richard Biener >> wrote: >> >> On Fri, May 16, 2014 at 12:07 PM, Thomas Preud'homme >> wrote: >>> Ping? >> >> Sorry ... >> >>> Best regards, >>> >>> Thomas Preud'homme >>> -Original Message- From: gc

Re: [PATCH, libstdc++/61166] overflow when parse number in std::duration operator""

On 15/05/14 22:54 -0400, Ed Smith-Rowland wrote: On 05/15/2014 03:03 PM, Jonathan Wakely wrote: Here's a finished patch to simplify Tested x86_64-linux. Ed, any objection to this version? This looks great, thanks! I committed that to trunk, I'll put it on the 4.9 branch too. Having done t

Re: [PATCH] Fix PR54733 Optimize endian independent load/store

On Fri, May 16, 2014 at 1:03 PM, Richard Biener wrote: > On Fri, May 16, 2014 at 12:56 PM, wrote: >> >> >>> On May 16, 2014, at 3:48 AM, Richard Biener >>> wrote: >>> >>> On Fri, May 16, 2014 at 12:07 PM, Thomas Preud'homme >>> wrote: Ping? >>> >>> Sorry ... >>> Best regards, >

[PATCH] Fix one testcase from PR61194

This fixes the non-regression testcase from PR61194 by also recognizing COND_EXPRs as sink for bool expressions in vectorizer pattern detection. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2014-05-16 Richard Biener PR tree-optimization/61194 * tree

PR 61084: Use widest_int in sparc_fold_builtin

This is the second part of PR 61084, which it seems I'd forgotten to post. pdist calculates a wide result from narrower inputs, so I should have used widest_int rather than wide_int. Tested by Rainer on SPARC Solaris. OK to install? Thanks, Richard gcc/ PR target/61084 * config

Re: [PATCH, AArch64] Use MOVN to generate 64-bit negative immediates where sensible

On 08/05/14 18:36, Ian Bolton wrote: > Hi, > > It currently takes 4 instructions to generate certain immediates on > AArch64 (unless we put them in the constant pool). > > For example ... > > long long > beefcafebabe () > { > return 0xBEEFCAFEBABEll; > } > > leads to ... >

Re: [PATCH (for next stage 1)] Add return type to gimple function dumps

On Tue, Apr 29, 2014 at 5:01 PM, David Malcolm wrote: > On Tue, 2014-04-29 at 11:16 +0200, Richard Biener wrote: >> On Tue, Apr 29, 2014 at 2:58 AM, David Malcolm wrote: >> > On Thu, 2014-04-24 at 15:46 -0600, Jeff Law wrote: >> >> On 03/10/14 13:22, David Malcolm wrote: >> >> > Gimple function d

Re: [PATCH, PR52252] Vectorization for load/store groups of size 3.

The test uses SSSE3 because of the following restriction in i386.c: static bool expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d) { rtx rperm[2][16], vperm, l, h, op, m128; unsigned int i, nelt, eltsz; if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16) return false; Does the foll

Re: [PATCH, PR52252] Vectorization for load/store groups of size 3.

Hi Evgeny, > Does the following fix ok? > > 2014-05-16 Evgeny Stupachenko > >* gcc.dg/vect/pr52252-ld.c: Fix target for the test. > > > diff --git a/gcc/testsuite/gcc.dg/vect/pr52252-ld.c > b/gcc/testsuite/gcc.dg/vect/pr52252-ld.c > index 6e3cb52..301433b 100644 > --- a/gcc/testsuite/gc

Re: patch8.diff updated Was: Re: GCC's -fsplit-stack disturbing Mach's vm_allocate

On Fri, May 16, 2014 at 1:03 AM, Svante Signell wrote: > > For that part of the patch without it the build on GNU/Hurd fails. On > the other hand SYS_FCNTL is not defined for e.g. GNU/Linux either. This > is used in gcc-4.9-4.9.0/src/libgo/go/net/fd_unix.go: > func dupCloseOnExec(fd int) (newfd in

Re: [PATCH, PR52252] Vectorization for load/store groups of size 3.

On Fri, May 16, 2014 at 03:11:05PM +0200, Rainer Orth wrote: > Hi Evgeny, > > > Does the following fix ok? > > > > 2014-05-16 Evgeny Stupachenko > > > >* gcc.dg/vect/pr52252-ld.c: Fix target for the test. > > > > > > diff --git a/gcc/testsuite/gcc.dg/vect/pr52252-ld.c > > b/gcc/testsuit

Re: [PATCH, PR52252] Vectorization for load/store groups of size 3.

I'm not sure about other architectures. I can test it on x86. Most likely it will pass on Arm, but again I'm not sure that { arm*-*-* } is ok. The test is on general changes. So we can wait for others and if there are no more objections leave sparc-sun-solaris2 as target to skip. Or change to the

Re: [PATCH, PR52252] Vectorization for load/store groups of size 3.

Evgeny Stupachenko writes: > The test is on general changes. So we can wait for others and if there > are no more objections leave sparc-sun-solaris2 as target to skip. If so, use sparc*-*-* instead. > Or change to the following: > /* { dg-skip-if "The test should pass on x86, other architectur

Re: patch8.diff updated Was: Re: GCC's -fsplit-stack disturbing Mach's vm_allocate

On Fri, 2014-05-16 at 06:20 -0700, Ian Lance Taylor wrote: > On Fri, May 16, 2014 at 1:03 AM, Svante Signell > wrote: > > > > For that part of the patch without it the build on GNU/Hurd fails. On > > the other hand SYS_FCNTL is not defined for e.g. GNU/Linux either. This > > is used in gcc-4.9-4.9

Re: [PATCH] [PING^2] Fix for PR libstdc++/60758

On 07.05.2014 13:28, Ramana Radhakrishnan wrote: On 05/07/14 09:19, Yury Gribov wrote: Original Message Subject: [PING] [PATCH] Fix for PR libstdc++/60758 Date: Thu, 17 Apr 2014 17:48:12 +0400 From: Alexey Merzlyakov To: Ramana Radhakrishnan CC: gcc-patches@gcc.gnu.org , Viac

Re: avx runtime check

On May 15, 2014, at 11:52 PM, Richard Biener wrote: > On May 16, 2014 4:47:11 AM CEST, Mike Stump wrote: >> This reorders the avx checks and gates on a target triplet check before >> compiling any code. > > Can you explain why? Sure, because check_avx_hw_available runs [istarget x86_64-*-*] ||

[PATCH][ARM] Vectorize bswap[16,32,64] operations

Hi all, This is the aarch32 version of https://gcc.gnu.org/ml/gcc-patches/2014-04/msg00850.html that allows us to (auto-)vectorise the __builtin_bswap[16,32,64] functions using the vrev instructions. For that we create some new NEON builtins and get arm_builtin_vectorized_function to map to t

Re: [Committed] [PATCH,*/2] shrink wrap a function with a single loop: split live_edge

> One of the two commits breaks several fortran tests in 32 bit mode, ... It it is not the default you need to compile the failing tests with -mtune=core2 or -mtune=corei7. Dominique

[patch] fix recent libstdc++ test failures

Tested x86_64-linux, -m32 and -m64, committed to trunk. commit c5265e76b75cbfa0744c354f6d5aaf98c327ff8e Author: Jonathan Wakely Date: Fri May 16 13:26:18 2014 +0100 * testsuite/20_util/make_unsigned/requirements/typedefs-1.cc: Fix test for 32-bit target. * testsuite/20_util/mak

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Fri, May 16, 2014 at 12:51 PM, Richard Biener wrote: > Btw, the bswap pass enhancements that are currently in review may > also be an opportunity to catch these. They can merge adjacent > loads that are used "composed" (but not yet composed by storing > into adjacent memory). The basic-block v

Re: [GCC RFC]A new and simple pass merging paired load store instructions

> > Btw, the bswap pass enhancements that are currently in review may > also be an opportunity to catch these. They can merge adjacent > loads that are used "composed" (but not yet composed by storing > into adjacent memory). The basic-block vectorizer should also > handle this (if the compositio

[PATCH 0/5] let gdb reuse gcc'c C compiler

Hi! This patch series is half of a project to let gdb reuse gcc (which half depends on which list you are seeing this on), so that users can compile small snippets of code and evaluate them in the current context of the inferior. This first series implements this idea for C. A user can compile a

[PATCH 1/5] export finish_bitfield_layout from stor-layout

The gdb plugin handles some aspects of type layout on its own. It does this because it knows the layout of types, but not the path by which the layout was determined -- so normal gcc things like TYPE_PACKED cannot be used. This patch exposes one bit of stor-layout so it can be used by the plugin.

[PATCH 3/5] introduce the binding oracle

gdb wants to supply any declarations that may be referred to by the user's code. Hooking into symbol lookup was an efficient way to accomplish this. This patch introducing a "binding oracle" that is consulted whenever a symbol binding is looked up for the first time. The oracle is just a global

[PATCH 4/5] add gcc/gdb interface files

The gcc plugin is split into two parts. One part is an ordinary gcc plugin. The other part is a shared library that is loaded by gdb. This patch adds some files that define the interface exported by this shared library to gdb. These files also define the internal API by which the gdb- and gcc-s

Re: add dbgcnt and opt-info support for devirtualization

On Fri, May 16, 2014 at 4:00 AM, Richard Biener wrote: > On Fri, May 16, 2014 at 1:54 AM, Xinliang David Li wrote: >> Hi, debugging runtime bugs due to devirtualization can be hard for >> very large C++ programs with complicated class hierarchy. This patch >> adds the support to report this high

[PATCH 2/5] c_diagnostic_ignored_function hack

In the typical case, when compiling a snippet of user code, gdb wraps the user's text in a dummy function. It's somewhat odd for users if an error in their code is mentioned as coming from this dummy function. This patch makes it possible to suppress the function-name display in a straightforward

[C++ Patch] PR 51640

Hi, the main issue in the bug report is luckily already fixed in mainline and 4.9 (had to do with a commit of mine ;( but I think we can do a little better in the diagnostic: avoid the final redundant "does not name a type" error after the error message about ambiguity. Tested x86_64-linux.

Re: [PATCH] Implement -fsanitize=float-cast-overflow

On Fri, 16 May 2014, Jakub Jelinek wrote: > has variable. Guess the combination of IBM long double and __int128_t > (for long long it is still ok) is rare enough that we don't need to care > about it (alternative would be e.g. to compare against addition of There are existing problems with that

Re: add dbgcnt and opt-info support for devirtualization

> Hi, debugging runtime bugs due to devirtualization can be hard for > very large C++ programs with complicated class hierarchy. This patch > adds the support to report this high level transformation via > -fopt-info (not hidden inside dump file) and the ability the do binary > search with cutoff.

Re: [PATCH 2/5] c_diagnostic_ignored_function hack

On Fri, 16 May 2014, Tom Tromey wrote: > In the typical case, when compiling a snippet of user code, gdb wraps > the user's text in a dummy function. > > It's somewhat odd for users if an error in their code is mentioned as > coming from this dummy function. > > This patch makes it possible to s

Re: add dbgcnt and opt-info support for devirtualization

On Fri, May 16, 2014 at 9:03 AM, Jan Hubicka wrote: >> Hi, debugging runtime bugs due to devirtualization can be hard for >> very large C++ programs with complicated class hierarchy. This patch >> adds the support to report this high level transformation via >> -fopt-info (not hidden inside dump f

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On 05/16/14 04:07, Bin.Cheng wrote: On Fri, May 16, 2014 at 1:13 AM, Jeff Law wrote: On 05/15/14 10:51, Mike Stump wrote: On May 15, 2014, at 12:26 AM, bin.cheng wrote: Here comes up with a new GCC pass looking through each basic block and merging paired load store even they are not adjace

Re: [PATCH (for next stage 1)] Add return type to gimple function dumps

On Fri, 2014-05-16 at 14:59 +0200, Richard Biener wrote: > On Tue, Apr 29, 2014 at 5:01 PM, David Malcolm wrote: > > On Tue, 2014-04-29 at 11:16 +0200, Richard Biener wrote: > >> On Tue, Apr 29, 2014 at 2:58 AM, David Malcolm wrote: > >> > On Thu, 2014-04-24 at 15:46 -0600, Jeff Law wrote: > >> >

Re: [patch,mips] avoid invalid register for JALR

On Wed, 14 May 2014, Sandra Loosemore wrote: > > > When I was trying to benchmark another patch (which I'll be sending > > > along shortly) with CSiBE for -mabi=64, I ran into an assembler error > > > like this: > > > > > > /tmp/ccJv2faG.s: Assembler messages: > > > /tmp/ccJv2faG.s:1605: Error: a

Re: [PATCH 0/5] let gdb reuse gcc'c C compiler

On May 16, 2014, at 8:26 AM, Tom Tromey wrote: > This patch series is half of a project to let gdb reuse gcc (which > half depends on which list you are seeing this on), so that users can > compile small snippets of code and evaluate them in the current > context of the inferior. Nice… I looked

Re: [PATCH 2/5] c_diagnostic_ignored_function hack

> This patch makes it possible to suppress the function-name display in > a straightforward way: it adds a new global which the plugin can set > to declare the name of the dummy function. > > This patch seems like a bit of a hack, but there didn't seem to be a > notably cleaner approach. Can't you

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On 05/16/14 04:07, Bin.Cheng wrote: Yes, I think this one does have a good reason. The target independent pass just makes sure that two consecutive memory access instructions are free of data-dependency with each other, then feeds it to back-end hook. It's back-end's responsibility to generate

Re: [C++ Patch] PR 51640

OK. Jason

Re: add dbgcnt and opt-info support for devirtualization

> > I have been chasing a runtime failure of a very large test built with > gcc-4_9. The bad code either calls a pure function or turn a virtual > call into __builtin_unreachable (incomplete target set). The indirect > info shows the otr type to be !maybe_derived_type, and the outer-type > gets cl

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On May 16, 2014, at 3:07 AM, Bin.Cheng wrote: > >> I don't see how regrename will help resolve [base+offset] false >> dependencies. Can you explain? I'd expect effects from >> hardreg-copyprop "commoning" a base register. > It's the register operand's false dependency, rather than the base's > on

Re: we are starting the wide int merge

On Sat, 10 May 2014, Gerald Pfeifer wrote: > Since (at least) 16:40 UTC that day my i386-unknown-freebsd10.0 builds > fail as follows: > > Comparing stages 2 and 3 > warning: gcc/cc1obj-checksum.o differs > warning: gcc/cc1-checksum.o differs > warning: gcc/cc1plus-checksum.o differs > B

Re: RFA: Fix calculation of size of builtin setjmp buffer

>OK - here is your version of the patch, extended with a comment which > I think is helpful for other people reading the code, and with the > changes to builtins.c and md.texi removed, since the size of the buffer > is not changing. > >Is this version OK to apply ? Yes, IMO that's fine, t

Re: RFA: Fix calculation of size of builtin setjmp buffer

> But, fails whenever the size of the mode of the save area is bigger than a > certain amount… On my port, the size taken up by the save area is large > enough to cause this to fail. :-( That's a bit unexpected, why do you need so big a save area exactly? The only architecture for which this

Re: [PATCH] Fix ARM NAN fraction bits

On Thu, 27 Feb 2014, Joey Ye wrote: > Current ARM soft-float implementation is violating the RTABI > (http://infocenter.arm.com/help/topic/com.arm.doc.ihi0043d/IHI0043D_rtabi.pd > f) Section 4.1.1.1: > > When not otherwise specified by IEEE 754, the result on an invalid operation > should be the

Re: [PATCH] Fix PR54733 Optimize endian independent load/store

> On May 16, 2014, at 4:13 AM, Richard Biener > wrote: > > On Fri, May 16, 2014 at 1:03 PM, Richard Biener > wrote: >> On Fri, May 16, 2014 at 12:56 PM, wrote: >>> >>> On May 16, 2014, at 3:48 AM, Richard Biener wrote: On Fri, May 16, 2014 at 12:07 PM, Thomas Preud'

Re: [PATCH] Fix ARM NAN fraction bits

On Fri, 16 May 2014, Maciej W. Rozycki wrote: > 2014-05-16 Maciej W. Rozycki > > PR libgcc/60166 > * sysdeps/arm/soft-fp/sfp-machine.h (_FP_NANFRAC_S, _FP_NANFRAC_D) > (_FP_NANSIGN_Q): Set the quiet bit. OK for glibc. -- Joseph S. Myers jos...@codesourcery.com

Re: PR 61084: Use widest_int in sparc_fold_builtin

> This is the second part of PR 61084, which it seems I'd forgotten to post. > pdist calculates a wide result from narrower inputs, so I should have > used widest_int rather than wide_int. Is that documented? Because, if even you wide-int guys got it wrong... > PR target/61084 > * co

Re: [PATCH][1/n][RFC] Make FRE/PRE somewhat predicate aware

On 05/16/14 02:02, Richard Biener wrote: Quiet as usual. Which strongly suggests folks trust you to do the right thing here :-) I think the FRE/PRE reference in $SUBJECT made me ignore the patch entirely -- my brain hurts when I look at our tree PRE implementation. Jeff

Eliminate write-only variables

Hi, this patch adds code to remove write only static variables. While analyzing effectivity of LTO on firefox, I noticed that surprisingly large part of binary's data segment is occupied by these. Fixed thus. (this is quite trivial transformation, I just never considered it important enough to wo

Re: [PATCH] Use direct computation to calculate fallthrough edge count.

> This patch uses direct computation (instead of indirect minus > computation) to calculate fallthrough edge's count and frequency. This > is less error-prone when the profile is inconsistent (e.g. all succ > edge counts sums larger than bb count). > > Bootstrapped and regression test on-going. >

[PATCH] Use direct computation to calculate fallthrough edge count.

This patch uses direct computation (instead of indirect minus computation) to calculate fallthrough edge's count and frequency. This is less error-prone when the profile is inconsistent (e.g. all succ edge counts sums larger than bb count). Bootstrapped and regression test on-going. OK for trunk

Re: Eliminate write-only variables

Jan Hubicka writes: > + /* Remove stores to variables we marked readonly. s/read/write/ > + /* For calls we can simply remove LHS when it is known to be read > only. */ s/read/write/ Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 17

Re: Eliminate write-only variables

> Jan Hubicka writes: > > > + /* Remove stores to variables we marked readonly. > > s/read/write/ > > > + /* For calls we can simply remove LHS when it is known to be read > > only. */ > > s/read/write/ Ah, thanks! Honza > > Andreas. > > -- > Andreas Schwab, sch...@linux-m68k.or

Re: add dbgcnt and opt-info support for devirtualization

On Fri, May 16, 2014 at 9:51 AM, Jan Hubicka wrote: >> >> I have been chasing a runtime failure of a very large test built with >> gcc-4_9. The bad code either calls a pure function or turn a virtual >> call into __builtin_unreachable (incomplete target set). The indirect >> info shows the otr typ

patch to fix PR60969

The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60969 The patch was bootstrapped and tested on x86/x86-64. Committed as rev. 210519 to gcc 4.9 branch and as rev. 210520 to trunk. 2014-05-16 Vladimir Makarov PR rtl-optimization/60969 * ira-costs.c (r

[C++ patch] Reduce vtable alignment

Hi, compiling: struct A { virtual void foo(void) {}; virtual void foo2(void) {}; virtual void foo3(void) {}; virtual void foo4(void) {}; virtual void foo5(void) {}; } a; give 32 byte alignment to the virtual table on i386, because we bump up alignments of arrays to size of vector operat

Re: Avoiding some garbage rtl from instantiate_virtual_regs

On 05/16/14 02:47, Richard Sandiford wrote: It seems that in a typical -O0 compile the amount of rtl that starts out as needed but becomes garbage is only slightly less than half of the total amount created. One of the big offenders is the vregs pass, which creates new PLUSes when instanstiating

Re: [PATCH][1/n][RFC] Make FRE/PRE somewhat predicate aware

On May 16, 2014 7:07:11 PM CEST, Jeff Law wrote: >On 05/16/14 02:02, Richard Biener wrote: >>> >> Quiet as usual. >Which strongly suggests folks trust you to do the right thing here :-) > I think the FRE/PRE reference in $SUBJECT made me ignore the patch >entirely -- my brain hurts when I look

Re: [DOC Patch] Incorrect @xref in #pragma visibility

On 05/14/14 20:25, David Wohlferd wrote: 2014-05-14 David Wohlferd * doc/extend.texi: (Visibility Pragmas) Fix misplaced @xref Approved and installed on your behalf. Thanks, jeff

Re: [PATCH 1/1][ira-costs] grammar fix of comments

On 05/14/14 18:45, Zhouyi Zhou wrote: Fix grammar error for comments above process_bb_node_for_hard_reg_moves Signed-off-by: Zhouyi Zhou --- gcc/ira-costs.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index 648806b..fbfb070 1006

Re: [PATCH 1/5] export finish_bitfield_layout from stor-layout

On 05/16/14 09:26, Tom Tromey wrote: The gdb plugin handles some aspects of type layout on its own. It does this because it knows the layout of types, but not the path by which the layout was determined -- so normal gcc things like TYPE_PACKED cannot be used. This patch exposes one bit of stor-

Re: [PATCH 2/5] c_diagnostic_ignored_function hack

On 05/16/14 09:26, Tom Tromey wrote: In the typical case, when compiling a snippet of user code, gdb wraps the user's text in a dummy function. It's somewhat odd for users if an error in their code is mentioned as coming from this dummy function. This patch makes it possible to suppress the fun

Re: [PATCH 2/5] c_diagnostic_ignored_function hack

Jeff> BTW, didn't see patch #5 of the series. Maybe it was too big. I will try to resend it compressed. Tom

[PATCH 5/5] add libcc1

> "Tom" == Tom Tromey writes: Tom> This patch series is half of a project to let gdb reuse gcc (which Tom> half depends on which list you are seeing this on), so that users can Tom> compile small snippets of code and evaluate them in the current Tom> context of the inferior. Jeff noted that

Re: [C++ patch] Reduce vtable alignment

Hi, this patch makes also the rtti type info for A in the testcase: struct A { virtual void foo(void) {}; virtual void foo2(void) {}; virtual void foo3(void) {}; virtual void foo4(void) {}; virtual void foo5(void) {}; } a; aligned only to the ABI requirement (8) instead of being bumped

Re: [PATCH 3/5] introduce the binding oracle

On 05/16/14 09:26, Tom Tromey wrote: gdb wants to supply any declarations that may be referred to by the user's code. Hooking into symbol lookup was an efficient way to accomplish this. This patch introducing a "binding oracle" that is consulted whenever a symbol binding is looked up for the fi

Re: [patch] fix ppc spe bootstrap error in dwf_regno

On 04/30/14 09:15, Cesar Philippidis wrote: I've been working on a patch to switch a few ppc targets to use softfp in libgcc instead of fpbit and I noticed that ppc-none-eabispe fails to bootstrap in both trunk and 4.9. The regression was introduced in

Re: [PATCH, i386, Pointer Bounds Checker 2/x] Intel Memory Protection Extensions (MPX) instructions support

On 04/16/14 05:35, Ilya Enkovich wrote: Hi, This patch introduces Intel MPX bound registers and instructions. It was approved earlier for 4.9 and had no significant changes since then. I'll assume patch is OK if no objections arise. Patch was bootstrapped and tested for linux-x86_64. Thank

Re: [PATCH] Fix more typos in error messages

On 02/25/14 09:21, Benno Schulenberg wrote: 2014-02-07 Benno Schulenberg * config/arc/arc.c (arc_init): Fix typo in error message. * config/i386/i386.c (ix86_expand_builtin): Likewise. (split_stack_prologue_scratch_regno): Likewise. * fortran/check.c (gfc_check_

[patch, libstdc++] fix TCL error in abi.exp

As noted in PR 23867, the libstdc++ ABI testsuite doesn't work for installed compiler testing. There is some logic in abi.exp to check for the presence of the required bits and skip these tests if they're not there, but before it gets that far it's hitting a TCL error: ERROR: can't read "base

Re: Unreviewed Patch

On 02/22/14 16:07, rbmj wrote: Hi all, Just a ping, I haven't gotten anything back on this patch: http://gcc.gnu.org/ml/gcc-patches/2014-02/msg00621.html The patch needs to be tested by bootstrapping on another platform and performing a regression test.Most folks use an x86_64 linux system

Re: [patch, libstdc++] fix TCL error in abi.exp

On 05/16/14 13:53, Sandra Loosemore wrote: As noted in PR 23867, the libstdc++ ABI testsuite doesn't work for installed compiler testing. There is some logic in abi.exp to check for the presence of the required bits and skip these tests if they're not there, but before it gets that far it's hitt

Re: [PATCH][C-family] Fix PR61184

On 05/14/14 03:06, Richard Biener wrote: The following fixes pre/post-inc/dec gimplification of promoted integer types. There is the issue with the way TYPE_OVERFLOW_UNDEFINED is related to TYPE_OVERFLOW_WRAPS and the (non-)semantics of -fno-strict-overflow. In this case, with -On -fno-strict-

Re: [PATCH 5/5] add libcc1

On Fri, 16 May 2014, Tom Tromey wrote: > This patch adds the plugin to the gcc tree and updates the top-level > configury. I don't see anything obvious that would disable the plugin if plugins are unsupported (e.g. on Windows host) or disabled (--disable-plugin). Probably the relevant support

Re: [GCC RFC]A new and simple pass merging paired load store instructions

On Fri, 2014-05-16 at 18:10 +0800, Bin.Cheng wrote: > On Thu, May 15, 2014 at 6:31 PM, Oleg Endo wrote: > > > > How about the following. > > Instead of adding new hooks and inserting the pass to the general pass > > list, make the new > > pass class take the necessary callback functions directly.

[PATCH] Use optimize_function_for_size_p to assign register frequency

This patch uses optimize_function_for_size_p to replace old optimize_size check in regs.h and ira-int.h to make it consistent. Bootstrapped and testing on-going. OK for trunk if test passes? Thanks, Dehao gcc/ChangeLog: 2014-05-16 Dehao Chen * ira-int.h (REG_FREQ_FROM_EDGE_FREQ): Us

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