Re: update_vtable_references segfault

> On 12/12/15 09:44, Nathan Sidwell wrote: > >On 12/11/15 13:15, Jan Hubicka wrote: > >>>Jan, > > > >>>b) augment can_replace_by_local_alias_in_vtable to check whether > >>>aliases can be created? > >> > >>I think this is best: can_replace_by_local_alias_in_vtable exists to > >>prevent the >

Re: [PATCH] Fix PR c++/21802 (two-stage name lookup fails for operators)

Hi, On Mon, 14 Dec 2015, Patrick Palka wrote: > >>> >This should use cp_tree_operand_length. > >> Hmm, I don't immediately see how I can use this function here. It > >> expects a tree but I dont have an appropriate tree to give to it, only a > >> tree_code. > > > > True. So let's introduce

Re: [PATCH][combine] PR rtl-optimization/68651 Try changing rtx from (r + r) to (r << 1) to aid recognition

On 16/12/15 12:18, Bernd Schmidt wrote: On 12/15/2015 05:21 PM, Kyrill Tkachov wrote: Then for the shift pattern in the MD file we'd have to dynamically select the scheduling type depending on whether or not the shift amount is 1 and the costs line up? Yes. This isn't unusual, take a look at

Re: [PATCH][combine] PR rtl-optimization/68651 Try changing rtx from (r + r) to (r << 1) to aid recognition

On 12/16/2015 10:00 AM, Kyrill Tkachov wrote: On 16/12/15 12:18, Bernd Schmidt wrote: On 12/15/2015 05:21 PM, Kyrill Tkachov wrote: Then for the shift pattern in the MD file we'd have to dynamically select the scheduling type depending on whether or not the shift amount is 1 and the costs

Re: [PATCH][WIP] libstdc++: Make certain exceptions transaction_safe.

Sorry for the delay finishing this review, some of the code kept melting my brain ;-) On 14/11/15 20:45 +0100, Torvald Riegel wrote: diff --git a/libstdc++-v3/config/abi/pre/gnu.ver b/libstdc++-v3/config/abi/pre/gnu.ver index 1b3184a..d902b03 100644 --- a/libstdc++-v3/config/abi/pre/gnu.ver

Re: [PATCH] C and C++ FE: better source ranges for binary ops

On 12/16/2015 11:04 AM, David Malcolm wrote: Currently trunk emits range information for most bad binary operations in the C++ frontend; but not in the C frontend. The helper function binary_op_error shared by C and C++ takes a location_t. In the C++ frontend, a location_t containing the range

[PTX] function frame emission

This patch removes OUTGOING_STATIC_CHAIN_REGNUM -- there's no need for it to be distinct from STATIC_CHAIN_REGNUM. Also, when we have to emit a frame or outgoing args, but it's zero sized, there's no need to actually emit the frame or arg array. We can just initialize the appropriate register

Re: update_vtable_references segfault

On 12/12/15 09:44, Nathan Sidwell wrote: On 12/11/15 13:15, Jan Hubicka wrote: Jan, b) augment can_replace_by_local_alias_in_vtable to check whether aliases can be created? I think this is best: can_replace_by_local_alias_in_vtable exists to prevent the body walk in cases we are not going

[PATCH] Remove use of 'struct map' from plugin (nvptx)

Hi, The attached patch removes the use of the map structure (struct map) from the NVPTX plugin. Regtested on x86_64-pc-linux-gnu Ok for trunk? Thanks! Jim ChangeLog = 2015-12-XX James Norris libgomp/ * plugin/plugin-nvptx.c (struct map):

Re: [RFA] [PATCH] Fix invalid redundant extension elimination for rl78 port

On 12/01/2015 12:32 PM, Richard Sandiford wrote: Jeff Law writes: @@ -1080,6 +1070,18 @@ add_removable_extension (const_rtx expr, rtx_insn *insn, } } + /* Fourth, if the extended version occupies more registers than the +original and the

Re: [PATCH 2/4][AArch64] Increase the loop peeling limit

On 12/16/2015 05:24 AM, Richard Earnshaw (lists) wrote: On 15/12/15 23:34, Evandro Menezes wrote: On 12/14/2015 05:26 AM, James Greenhalgh wrote: On Thu, Dec 03, 2015 at 03:07:43PM -0600, Evandro Menezes wrote: On 11/20/2015 05:53 AM, James Greenhalgh wrote: On Thu, Nov 19, 2015 at

Re: [PATCH, PR67627][RFC] broken libatomic multilib parallel build

On 12/04/2015 05:39 AM, Szabolcs Nagy wrote: As described in pr other/67627, the all-multi target can be built in parallel with the %_.lo targets which generate make dependencies that are parsed during the build of all-multi. gcc -MD does not generate the makefile dependencies in an atomic way

Fix PR66208

This is a relatively straightforward PR where we should mention a macro expansion in a warning message. The patch below implements the suggestion by Marek to pass a location down from build_function_call_vec. Ok if tests pass on x86_64-linux? One question I have is about -Wformat, which is

C++ PATCH for c++/63628 (generic lambdas and variadic capture)

My patch for 63809 fixed non-capturing use of a parameter pack in a regular lambda, but not in a generic lambda, where we can't rely on being instantiated within the enclosing context. So we use the existing support for references to parameters from trailing return type, another situation

Re: ipa-cp heuristics fixes

On Wed, Dec 16, 2015 at 06:15:33PM +0100, Jan Hubicka wrote: > > On Wed, Dec 16, 2015 at 05:24:25PM +0100, Jan Hubicka wrote: > > > I am trying to understand Jakub's debug code and perhaps it can be > > > improved. But in > > > the case of optimized out unused parameters I think it is perfectly

Re: [PATCH, PR67627][RFC] broken libatomic multilib parallel build

On 12/04/2015 05:39 AM, Szabolcs Nagy wrote: As described in pr other/67627, the all-multi target can be built in parallel with the %_.lo targets which generate make dependencies that are parsed during the build of all-multi. gcc -MD does not generate the makefile dependencies in an atomic way

[PATCH] [graphite] update required isl version

we check for a the isl compute timeout function added in isl 0.13. That means GCC could still be configured with isl 0.13, 0.14, and 0.15. * config/isl.m4 (ISL_CHECK_VERSION): Check for isl_ctx_get_max_operations. * configure: Regenerate. gcc/ * config.in:

Re: ipa-cp heuristics fixes

> On Wed, Dec 16, 2015 at 05:24:25PM +0100, Jan Hubicka wrote: > > I am trying to understand Jakub's debug code and perhaps it can be > > improved. But in > > the case of optimized out unused parameters I think it is perfectly > > resonable to > > say that the variable was optimized out. > > As

[PATCH] C and C++ FE: better source ranges for binary ops

Currently trunk emits range information for most bad binary operations in the C++ frontend; but not in the C frontend. The helper function binary_op_error shared by C and C++ takes a location_t. In the C++ frontend, a location_t containing the range has already been built, so we get the

Re: [PATCH] Better error recovery for merge-conflict markers (v5)

On Wed, 2015-12-16 at 00:52 +0100, Bernd Schmidt wrote: > On 12/15/2015 08:30 PM, David Malcolm wrote: > > > I got thinking about what we'd have to do to support Perforce-style > > markers, and began to find my token-matching approach to be a little > > clunky (in conjunction with reading

[PATCH] [ARM] PR68532: Fix VUZP and VZIP recognition on big endian

Hi This patch addresses incorrect recognition of VEC_PERM_EXPRs as VUZP and VZIP on armeb-* targets. It also fixes the definition of the vuzpq_* and vzipq_* NEON intrinsics which use incorrect lane specifiers in the use of __builtin_shuffle(). The problem with arm_neon.h can be seen by

Re: [PATCH] Better error recovery for merge-conflict markers (v4)

On Wed, 2015-12-09 at 18:44 +0100, Bernd Schmidt wrote: > On 12/09/2015 05:58 PM, David Malcolm wrote: > > On Wed, 2015-11-04 at 14:56 +0100, Bernd Schmidt wrote: > >> > >> This seems like fairly low impact but also low cost, so I'm fine with it > >> in principle. I wonder whether the length of

Fix size of enum bitfield in recently added test

Matthew pointed out this test was failing for arm-none-eabi because the rtx_code enum is represented in 8 bits which causes this error: pr68619-4.c:42:17: error: width of 'code' exceeds its type enum rtx_code code:16; I changed the size of the bitfield in the obvious way. I verified all

Re: ipa-cp heuristics fixes

Hi, just to summarize a discussion on IRC. The problem is that we produce debug statements for eliminated arguments only in ipa-sra and ipa-split, while we don't do anything for cgraph clones. This is a problem on release branches, too. It seems we have all the necessary logic, but the callee

Re: [RFA] [PATCH] Fix invalid redundant extension elimination for rl78 port

On 12/01/2015 12:32 PM, Richard Sandiford wrote: Jeff Law writes: @@ -1080,6 +1070,18 @@ add_removable_extension (const_rtx expr, rtx_insn *insn, } } + /* Fourth, if the extended version occupies more registers than the +original and the

Last testcase for PR middle-end/25140

Hi, I checked the ipa-pta and pta implementations and these seems to work just fine with presence of aliases because get_constraint_for_ssa_var already looks into the alias targets. This patch adds a testcase I constructed. Since I am done with auditing *alias*.c for variable aliases I will

Re: [PATCHES, PING*5] Enhance standard DWARF for Ada

On 12/16/2015 03:53 AM, Pierre-Marie de Rodat wrote: + /* Called from finalize_size_functions for functions whose body is needed to + generate complete debug info. For instance, functions used to compute the + size of variable-length structures. */ + void (* function_body) (tree

Re: [PATCH][AArch64] Replace insn to zero up DF register

On 10/30/2015 05:24 AM, Marcus Shawcroft wrote: On 20 October 2015 at 00:40, Evandro Menezes wrote: In the existing targets, it seems that it's always faster to zero up a DF register with "movi %d0, #0" instead of "fmov %d0, xzr". This patch modifies the respective

Re: [PATCH] Fix PR c++/21802 (two-stage name lookup fails for operators)

On 2015.12.14 at 19:34 -0500, Jason Merrill wrote: > OK. This patch caused https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68936 -- Markus

[PATCH] Fix INTEGER_CST handling for > 64 bits wide bitfields (PR tree-optimization/68835)

Hi! As can be seen on the testcases below, on > 64 bit precision bitfields we either ICE or miscompile. get_int_cst_ext_nunits already has code that for unsigned precision in multiplies of HOST_BITS_PER_WIDE_INT it forces TREE_INT_CST_EXT_NUNITS to be bigger than TREE_INT_CST_NUNITS, the former

[PATCH] PR target/68937: i686: -fno-plt produces wrong code (maybe only with tailcall

Since sibcall never returns, we can only use call-clobbered register as GOT base. Otherwise, callee-saved register used as GOT base won't be properly restored. Tested on x86-64 with -m32. OK for trunk? H.J. --- gcc/ PR target/68937 * config/i386/i386.c

[v3 PATCH] PR libstdc++/68276

Tested on Linux-PPC64. 2015-12-17 Ville Voutilainen PR libstdc++/68276 * src/c++11/ios.cc (_M_grow_words): Use nothrow new. * testsuite/27_io/ios_base/storage/11584.cc: Adjust. diff --git a/libstdc++-v3/src/c++11/ios.cc b/libstdc++-v3/src/c++11/ios.cc

Re: [PATCH] Fix some blockers of PR c++/24666 (arrays decay to pointers too early)

On 12/15/2015 04:16 PM, Patrick Palka wrote: + if (MAYBE_CLASS_TYPE_P (type)) +; What does this patch do with conversion to const reference to class? I think we want to check MAYBE_CLASS_TYPE_P (non_reference (type)) here. Jason

Re: Fix PR66208

On 12/16/2015 10:13 AM, Bernd Schmidt wrote: This is a relatively straightforward PR where we should mention a macro expansion in a warning message. The patch below implements the suggestion by Marek to pass a location down from build_function_call_vec. Ok if tests pass on x86_64-linux? One

[PATCH] [graphite] move all isl include files to graphite.h

* graphite-dependences.c: Move all isl include files to... * graphite-isl-ast-to-gimple.c: Same. * graphite-optimize-isl.c: Same. * graphite-poly.c: Same. * graphite-scop-detection.c: Same. * graphite.c: Same. * graphite.h: ... here. ---

Re: [PATCH] Fix PR c++/21802 (two-stage name lookup fails for operators)

On Wed, 16 Dec 2015, Michael Matz wrote: Hi, On Mon, 14 Dec 2015, Patrick Palka wrote: This should use cp_tree_operand_length. Hmm, I don't immediately see how I can use this function here. It expects a tree but I dont have an appropriate tree to give to it, only a tree_code. True. So

Re: ISL version check patch

On 12/16/2015 02:22 PM, Nathan Sidwell wrote: This patch https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01273.html breaks builds using static libisl & libgmp. (a whole slew of undefined __gmpz_FOO symbols). Fixed with the attached patch to add -lgmp etc to the isl link test. ok? OK. jeff

libgcc: unwind-ia64.c without malloc/free

Hi, this is just an idea, how to avoid use of malloc in unwind-ia64.c. I can compile this with my cross-compiler, but can not test anything. If you find it interesting, then someone should continue this work and test and/or fix it until it really works. The idea is, I can use alloca instead of

[PATCH] Pr 68805, Fix PowerPC little endian -mvsx-timode

My first mail did not seem to be delivered, so I'm trying again. This fixes a bug with the debug switch -mvsx-timode that we would eventually like to enable by default on PowerPC little endian server systems. The bug is that the load with rotate or rotate with store instructions needed on power8

Re: [PATCH] Pr 68805, Fix PowerPC little endian -mvsx-timode

On Wed, Dec 16, 2015 at 6:20 PM, Michael Meissner wrote: > My first mail did not seem to be delivered, so I'm trying again. > > This fixes a bug with the debug switch -mvsx-timode that we would eventually > like to enable by default on PowerPC little endian server

ISL version check patch

This patch https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01273.html breaks builds using static libisl & libgmp. (a whole slew of undefined __gmpz_FOO symbols). Fixed with the attached patch to add -lgmp etc to the isl link test. ok? nathan 2015-12-16 Nathan Sidwell *

Re: [PATCH] Fix PR c++/21802 (two-stage name lookup fails for operators)

Looks good. Jason

Re: [PATCH] Fix some blockers of PR c++/24666 (arrays decay to pointers too early)

On Wed, 16 Dec 2015, Jason Merrill wrote: On 12/15/2015 04:16 PM, Patrick Palka wrote: + if (MAYBE_CLASS_TYPE_P (type)) +; What does this patch do with conversion to const reference to class? I think we want to check MAYBE_CLASS_TYPE_P (non_reference (type)) here. That makes sense.

[PATCH] [graphite] attach schedule tree to the scop

we used to translate the just computed schedule tree into a union_map, and then in the code generation it would be translated back to a schedule tree just before generating AST code. --- gcc/graphite-isl-ast-to-gimple.c | 65 ++-- gcc/graphite-optimize-isl.c

Re: [v3 PATCH] PR libstdc++/68276

On 17 December 2015 at 00:12, Ville Voutilainen wrote: > Tested on Linux-PPC64. > > 2015-12-17 Ville Voutilainen > > PR libstdc++/68276 > > * src/c++11/ios.cc (_M_grow_words): Use nothrow new. > *

Re: [gomp4] [WIP] OpenACC bind, nohost clauses

On 12/14/2015 12:36 PM, Cesar Philippidis wrote: > On 12/08/2015 11:55 AM, Thomas Schwinge wrote: >> On Sat, 14 Nov 2015 09:36:36 +0100, I wrote: >> C front end: >> >> --- gcc/c/c-parser.c >> +++ gcc/c/c-parser.c >> @@ -11607,6 +11607,8 @@ c_parser_oacc_clause_async (c_parser *parser,

Re: [ARM] Use vector wide add for mixed-mode adds

Kyrill, I have attached a patch that address your comments. The only change I would ask you to re-consider renaming is the function 'bool aarch32_simd_check_vect_par_cnst_half'. This function was copied from the aarch64 port and I thought it as important to match the naming for maintenance

[PATCH] C FE: improvements to ranges of bad return values

In the C FE, c_parser_statement_after_labels passes "xloc" to c_finish_return, which is the location of the first token within the returned expression. Hence we don't get a full underline for the following: diagnostic-range-bad-return.c:34:10: warning: function returns address of local variable

[PATCH, GCC, V8M 0/6] Add support for ARMv8-M

Hi, I'll be posting a patch series intended for trunk whose aim is to add support for ARMv8-M. This patch series does not include changes to support the security extensions [nor does it include atomics for ARMv8-M Baseline]. This will be posted as a separate patch series. === Quick overview

[arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

Hi, We decided to apply the following patch to the ARM embedded 5 branch. This is *not* intended for trunk for now. We will send a separate email for trunk. This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This specific patch fixes some assumptions related to M

RE: [arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

The following was committed, once rebased on top of the embedded branch (patch was generated on top of gcc-5-branch): diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8c10ea3c9053e89b8eae1e5353b92d6020499409..bf1a0e874b1669f3ebe1e5870556a46b80686b82 100644 ---

[PATCH, ARM 2/6] Add support for ARMv8-M

Hi, This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This specific patch adds basic support for the new architecture, allowing the new names to be accepted by -march and the compiler to behave like ARMv6-M (for ARMv8-M Baseline) and or ARMv7-M (for ARMv8-M Mainline).

[committed] Fix HPPA/PARISC 32-bit Linux kernel build

The attached patch fixes a reload error in one of the new 64-bit atomic patterns in a 32-bit kernel build. Kernel builds disable the use of floating point registers with -mdisable-fpregs. The atomic patterns need to use floating point loads and stores and should have been disabled when

Re: [PATCH] Fix some blockers of PR c++/24666 (arrays decay to pointers too early)

OK, thanks. Jason

Re: [build] Only support -gstabs on Mac OS X if assember supports it (PR target/67973)

Mike Stump writes: > On Dec 15, 2015, at 5:35 AM, Rainer Orth > wrote: >> Right: I'm effectively keeping just the first configure test for .stabs >> support in the assembler to enable or disable >> DBX_DEBUG/DBX_DEBUGGING_INFO. I'll post

[gomp4] Merge trunk r231689 (2015-12-16) into gomp-4_0-branch

Hi! Committed to gomp-4_0-branch in r231738: commit d0b110f2163a5b186f15d05c9bfc6f51a42d652c Merge: 2a5a682 565bc8f Author: tschwinge Date: Thu Dec 17 07:11:02 2015 + svn merge -r 231118:231689 svn+ssh://gcc.gnu.org/svn/gcc/trunk

[arm-embedded][PATCH, ARM 2/6] Add support for ARMv8-M

Hi, We decided to apply the following patch to the ARM embedded 5 branch. Best regards, Thomas > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Thursday, December 17, 2015 3:25 PM > To:

RE: [PATCH, ARM 3/6] Fix indentation of FL_FOR_ARCH* definition after adding support for ARMv8-M

[Fixed the subject and added ARM maintainers to recipient.] > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Thursday, December 17, 2015 3:51 PM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH, ARM

[arm-embedded][PATCH, ARM 3/6] Fix indentation of FL_FOR_ARCH* definition after adding support for ARMv8-M

Hi, We decided to apply the following patch to the ARM embedded 5 branch. Best regards, Thomas > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Thursday, December 17, 2015 3:51 PM > To:

[PATCH, ARM 3/8] Fix indentation of FL_FOR_ARCH* definition after adding support for ARMv8-M

Hi, This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This specific patch fixes the indentation of FL_FOR_ARCH* macros definition following the patch to add support for ARMv8-M. Since this is an obvious change, I'm not expecting a review and will commit it as soon as

[PATCH, ARM, 3/3] Add multilib support for bare-metal ARM architectures

Hi Ramana, As suggested in your initial answer to this thread, we updated the multilib patch provided in ARM's embedded branch to be up-to-date with regards to supported CPUs in GCC. As to the need to modify Makefile.in and configure.ac, this is because the patch aims to let control to the

[PATCH] Fix PR68915

The following will hopefully resolve PR68915 tested on x86_64-linux, applied. Richard. 2015-12-16 Richard Biener PR testsuite/68915 * gcc.dg/vect/pr46032.c: Use dg-additional-options. Index: gcc/testsuite/gcc.dg/vect/pr46032.c

Re: [PATCH 2/4][AArch64] Increase the loop peeling limit

On Wed, Dec 16, 2015 at 12:24 PM, Richard Earnshaw (lists) wrote: > On 15/12/15 23:34, Evandro Menezes wrote: >> On 12/14/2015 05:26 AM, James Greenhalgh wrote: >>> On Thu, Dec 03, 2015 at 03:07:43PM -0600, Evandro Menezes wrote: On 11/20/2015 05:53 AM, James

[RFC][PATCH] Fix broken handling of LABEL_REF in genrecog + genpreds.

The attached patch fixes the handling of LABEL_REF in genrecog and genpreds. The current code assumes that X can have only a mode than PRED (X, MODE) if X is CONST_INT, CONST_DOUBLE or CONST_WIDE_INT, but actually that can be also the case for a LABEL_REF with VOIDmode. Due to this it is

Re: [0/7] Type promotion pass and elimination of zext/sext

On Thu, Dec 10, 2015 at 1:27 AM, Kugan wrote: > Hi Riachard, > > Thanks for the reviews. > > I think since we have some unresolved issues here, it is best to aim for > the next stage1. I however would like any feedback so that I can > continue to improve this.

Re: [PATCH PR68542]

On Fri, Dec 11, 2015 at 3:03 PM, Yuri Rumyantsev wrote: > Richard. > Thanks for your review. > I re-designed fix for assert by adding additional checks for vector > comparison with boolean result to fold_binary_op_with_conditional_arg > and remove early exit to

Re: [PATCH] Fix Fortran deviceptr clause.

Hi, This is an update of my previous patch. Cesar (thanks!) pointed out some issues with the original patch that have now been addressed. Regtested on x86_64 OK for trunk? Thanks! Jim diff --git a/gcc/fortran/openmp.c b/gcc/fortran/openmp.c index 276f2f1..9350dc4 100644 ---

Re: [RFC] Request for comments on ivopts patch

On Tue, Dec 15, 2015 at 12:06 AM, Steve Ellcey wrote: > On Mon, 2015-12-14 at 09:57 +0100, Richard Biener wrote: > >> I don't know enough to assess the effect of this but >> >> 1) not all archs can do auto-incdec so either the comment is misleading >> or the test should

[PATCH, obvious, i386] Remove duplicate check for CLZERO.

Hello, ix86_target_macros_internal () contains duplicated check of `clzero' option. I've committed to main trunk as obvious patch in the bottom. gcc/ * config/i386/i386-c.c (ix86_target_macros_internal): Remove duplicate check (__CLZERO__). -- Thanks, K Index:

[PTX] simplify calling struct

PTX's machine_function structure squirrels away the function type to calculate the presence of varadic args later, rather than calculate it immediately. It also uses an rtx field as a boolean. This patch reorganizes it with less verbose names and more apt types. I also noticed that

Re: [PATCH] C FE: fix range of primary-expression in c_parser_postfix_expression

On Tue, Dec 15, 2015 at 09:11:38PM -0500, David Malcolm wrote: > In the C frontend, > c_parser_postfix_expression > after parsing a primary expression passes "loc", the location of the > *first token* in that expression to > c_parser_postfix_expression_after_primary, > which thus discards any

RE: [PATCH][AArch64] Add vector permute cost

Richard Biener wrote: > On Wed, Dec 16, 2015 at 10:32 AM, James Greenhalgh > wrote: > > On Tue, Dec 15, 2015 at 11:35:45AM +, Wilco Dijkstra wrote: > >> > >> Add support for vector permute cost since various permutes can expand into > >> a complex > >> sequence of

[PATCH PR68906]

Hi All, Here is simple patch which cures the issue with outer-loop unswitching - added invocation of number_of_latch_executions() to reject unswitching for non-iterated loops. Bootstrapping and regression testing did not show any new failures. Is it OK for trunk? ChangeLog: 2014-12-16 Yuri

Re: [PATCH][combine] PR rtl-optimization/68651 Try changing rtx from (r + r) to (r << 1) to aid recognition

On 12/15/2015 05:21 PM, Kyrill Tkachov wrote: Then for the shift pattern in the MD file we'd have to dynamically select the scheduling type depending on whether or not the shift amount is 1 and the costs line up? Yes. This isn't unusual, take a look at i386.md where you have a lot of switches

Re: [PATCH] Allow embedded timestamps by C/C++ macros to be set externally (2)

On 12/14/2015 03:31 PM, Dhole wrote: The copyright assignment process is now complete :) Let me know if I'm required to do anything else regarding the patch I sent. Right now we're in a bug fixing stage; please wait until stage 1 reopens and then resend your patch. Bernd

Re: [RFC, rtl optimization]: Better heuristics for estimate_reg_pressure_cost in presence of call for LICM.

On 12/16/2015 12:54 PM, Ajit Kumar Agarwal wrote: The estimate on target_clobbered_registers based on the call_used arrays is not correct. This is the worst case heuristics on the estimate on target_clobbered_registers. This disables many of the loop Invariant code motion opportunities in

Re: [PATCH] S/390: Allow to use r1 to r4 as literal pool base.

Dominik Vogt wrote: > On Mon, Dec 14, 2015 at 04:08:32PM +0100, Ulrich Weigand wrote: > > I don't think that r1 is actually safe here. Note that it may be used > > (unconditionally) as temp register in s390_emit_prologue in certain cases; > > the upcoming split-stack code will also need to use r1

Re: [PATCH PR68906]

On Wed, Dec 16, 2015 at 1:14 PM, Yuri Rumyantsev wrote: > Hi All, > > Here is simple patch which cures the issue with outer-loop unswitching > - added invocation of number_of_latch_executions() to reject > unswitching for non-iterated loops. > > Bootstrapping and regression

Re: [RFC, rtl optimization]: Better heuristics for estimate_reg_pressure_cost in presence of call for LICM.

On 12/16/2015 12:54 PM, Ajit Kumar Agarwal wrote: /* If there is a call in the loop body, the call-clobbered registers are not available for loop invariants. */ + if (call_p) available_regs = available_regs - target_clobbered_regs; - + /* If we have enough registers, we

[PATCH] OpenACC documentation for libgomp

Hi, Attached is the patch to add OpenACC documentation for libgomp. Ok to commit to trunk? Thanks! Jim Index: libgomp.texi === --- libgomp.texi (revision 231662) +++ libgomp.texi (working copy) @@ -94,10 +94,25 @@ @comment

[PATCH] Fix PR68861

The following fixes the SLP miscompile in PR68861 which happens because we didn't think of stmts appering multiple times in a SLP node when doing the operand swapping support. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk. Richard. 2015-12-16 Richard Biener

Re: [PATCH] S/390: Allow to use r1 to r4 as literal pool base.

On Wed, Dec 16, 2015 at 01:51:45PM +0100, Ulrich Weigand wrote: > Dominik Vogt wrote: > > > r2 through r4 should be fine. [ Not sure if there will be many (any?) > > > cases > > > where one of those is unused but r5 isn't, however. ] > > > > This can happen if the function only uses register

Re: [PATCH 1/7][ARM] Add support for ARMv8.1.

On 10/12/15 11:02, Ramana Radhakrishnan wrote: On Thu, Dec 10, 2015 at 10:43 AM, Ramana Radhakrishnan wrote: On Mon, Dec 7, 2015 at 4:04 PM, Matthew Wahab wrote: Ping. Updated patch attached. Matthew On 26/11/15 15:55, Matthew Wahab

[PATCH] Fix PRs 68916 and 68914

Testisms, the easiest thing is to require vect_perm. Tested on x86_64-unknown-linux-gnu, applied. Richard. 2015-12-16 Richard Biener PR testsuite/68916 PR testsuite/68914 * gcc.dg/vect/pr45752.c: Require vect_perm and adjust expected dump.

Re: [PATCH] S/390: Allow to use r1 to r4 as literal pool base.

Dominik Vogt wrote: > On Wed, Dec 16, 2015 at 01:51:45PM +0100, Ulrich Weigand wrote: > > Dominik Vogt wrote: > > > > r2 through r4 should be fine. [ Not sure if there will be many (any?) > > > > cases > > > > where one of those is unused but r5 isn't, however. ] > > > > > > This can happen if

Re: [PATCH][AArch64] Properly cost zero_extend+ashift forms of ubfi[xz]

On Fri, Dec 04, 2015 at 09:30:45AM +, Kyrill Tkachov wrote: > Hi all, > > We don't handle properly the patterns for the [us]bfiz and [us]bfx > instructions when they > have an extend+ashift form. For example, the > *_ashl pattern. > This leads to rtx costs recuring into the extend and

Re: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS

On Wed, Dec 16, 2015 at 01:05:21PM +, Wilco Dijkstra wrote: > James Greenhalgh wrote: > > On Tue, Dec 15, 2015 at 10:54:49AM +, Wilco Dijkstra wrote: > > > ping > > > > > > > -Original Message- > > > > From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com] > > > > Sent: 06 November

[PATCH] Fix PR68870

This extends the previous fix for the CFG cleanup issue WRT dead SSA defs to properly avoid doing sth fancy with conditons in the first pass. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2015-12-16 Richard Biener PR

[PATCH] Fix PR68707, 67323

The following patch adds a heuristic to prefer store/load-lanes over SLP when vectorizing. Compared to the variant attached to the PR I made the STMT_VINFO_STRIDED_P behavior explicit (matching what you've tested). It's a heuristic that may end up vectorizing less loops or loops in a less

Re: C PATCH for c/64637 (better location for -Wunused-value)

On Wed, Dec 16, 2015 at 10:04:05AM -0500, David Malcolm wrote: > On Wed, 2015-12-16 at 15:58 +0100, Marek Polacek wrote: > > The following improves the location for "statement with no effect" warning > > by > > using the location of the expression if available. Can't use EXPR_LOCATION > > as >

Re: [PATCH][AArch64] Avoid emitting zero immediate as zero register

On Tue, Dec 15, 2015 at 11:17:35AM +, Wilco Dijkstra wrote: > ping > > > -Original Message- > > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > > Sent: 28 October 2015 17:33 > > To: GCC Patches > > Subject: [PATCH][AArch64] Avoid emitting zero immediate as zero register > > > >

Re: [PATCH, 4/16] Implement -foffload-alias

On 16/12/15 14:16, Richard Biener wrote: On Mon, 14 Dec 2015, Tom de Vries wrote: On 14/12/15 14:26, Richard Biener wrote: On Sun, 13 Dec 2015, Tom de Vries wrote: On 11/12/15 14:00, Richard Biener wrote: On Fri, 11 Dec 2015, Tom de Vries wrote: On 13/11/15 12:39, Jakub Jelinek wrote:

Re: C PATCH for c/64637 (better location for -Wunused-value)

On Wed, 2015-12-16 at 15:58 +0100, Marek Polacek wrote: > The following improves the location for "statement with no effect" warning by > using the location of the expression if available. Can't use EXPR_LOCATION as > *_DECLs still don't carry a location. Out of interest, does it emit sane

Re: C PATCH for c/64637 (better location for -Wunused-value)

On Wed, 2015-12-16 at 16:09 +0100, Marek Polacek wrote: > On Wed, Dec 16, 2015 at 10:04:05AM -0500, David Malcolm wrote: > > On Wed, 2015-12-16 at 15:58 +0100, Marek Polacek wrote: > > > The following improves the location for "statement with no effect" > > > warning by > > > using the location

Re: [PATCH PR68906]

Richard, Here is updated patch which includes (1) a test on exit proposed by you and (2) another test from PR68021 which is caught by new check on counted loop. Outer-loop unswitching is not performed for both new tests. Bootstrapping and regression testing did not show any new failures. Is it

Re: [PATCH PR68906]

On Wed, Dec 16, 2015 at 3:36 PM, Yuri Rumyantsev wrote: > Richard, > > Here is updated patch which includes (1) a test on exit proposed by > you and (2) another test from PR68021 which is caught by new check on > counted loop. Outer-loop unswitching is not performed for both

Re: [PATCH][AArch64] PR target/68696 FAIL: gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1

On Tue, Dec 08, 2015 at 09:21:29AM +, Kyrill Tkachov wrote: > Hi all, > > The test gcc.target/aarch64/vbslq_u64_1.c started failing recently due to > some tree-level changes. > This just exposed a deficiency in our xor-and-xor pattern for the vector > bit-select pattern: >

C PATCH for c/64637 (better location for -Wunused-value)

The following improves the location for "statement with no effect" warning by using the location of the expression if available. Can't use EXPR_LOCATION as *_DECLs still don't carry a location. Bootstrapped/regtested on x86_64-linux, ok for trunk? 2015-12-16 Marek Polacek

Re: [PATCH, IA64] Fix building a bare-metal ia64 compiler

On 16.12.2015 05:59, Bernd Edlinger wrote: > Hi, > > On 16.12.2015 00:55 Bernd Schmidt wrote: >> On 12/15/2015 10:13 PM, Bernd Edlinger wrote: >>> due to recent discussion on the basic asm, and the special handling >>> of ASM_INPUT in ia64, I tried to build a bare-metal cross-compiler >>> for

[Ping]Re: [AArch64] Simplify TLS pattern by hardcoding relocation modifiers into pattern

On 10/09/15 12:28, Jiong Wang wrote: TLS instruction sequences are always with fixed format, there is no need to use operand modifier, we can hardcode the relocation modifiers into instruction pattern, all those redundant checks in aarch64_print_operand can be removed. OK for trunk?

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