Re: [PATCH] Avoid 1x vectors in tree-vect-generic (PR rtl-optimization/69896)

On February 27, 2016 2:07:43 AM GMT+01:00, Bill Schmidt wrote: >Also tested with powerpc64le-unknown-linux-gnu native bootstrap with no >regressions, where it fixes this bug as well as the (reopened) PR69613. > >Bill > >On Sat, 2016-02-27 at 00:04 +0100, Jakub

Re: [PATCH] Avoid 1x vectors in tree-vect-generic (PR rtl-optimization/69896)

Also tested with powerpc64le-unknown-linux-gnu native bootstrap with no regressions, where it fixes this bug as well as the (reopened) PR69613. Bill On Sat, 2016-02-27 at 00:04 +0100, Jakub Jelinek wrote: > Hi! > > On ppc64, the widest (and only) supported vector mode for __int128 > element

Re: [PATCH][LRA]Don't generate reload for output scratch operand from reload instruction.

On 02/26/2016 07:54 AM, Renlin Li wrote: Hi all, I admit that, the title looks a little bit confusing. The situation is like this, To make insn_1 strict, lra generates a new insn_1_reload insn. In insn_1_reload, there is a scratch operand with this form clobber (match_scratch:MODE x "=") When

Re: [AArch64] Emit square root using the Newton series

On 02/26/16 17:42, Evandro Menezes wrote: On 02/26/16 08:59, James Greenhalgh wrote: On Mon, Feb 22, 2016 at 06:50:44PM -0600, Evandro Menezes wrote: In preparation for the patch adding the Newton series also for square root, I'd like to propose this patch changing the name of the existing

Re: [AArch64] Emit square root using the Newton series

On 02/26/16 08:59, James Greenhalgh wrote: On Mon, Feb 22, 2016 at 06:50:44PM -0600, Evandro Menezes wrote: In preparation for the patch adding the Newton series also for square root, I'd like to propose this patch changing the name of the existing tuning flag for the reciprocal square root.

[PATCH] Avoid 1x vectors in tree-vect-generic (PR rtl-optimization/69896)

Hi! On ppc64, the widest (and only) supported vector mode for __int128 element type is V1TImode, and there is a V1TImode or opcode and a couple of others, but IMNSHO it is highly undesirable to lower BLKmode (say 2xTI, 4xTI etc.) generic vectors to V1TI instead of TI, there are no advantages in

Re: [PATCH][AArch64] Replace insn to zero up DF register

On 02/26/16 06:37, Wilco Dijkstra wrote: Evandro Menezes wrote: I have a question though: is it necessary to add the "fp" and "simd" attributes to both movsf_aarch64 and movdf_aarch64 as well? You need at least the "simd" attribute, but providing "fp" as well is clearer

Re: [C PATCH] Fix C error-recovery (PR c/69796, PR c/69974)

On Fri, Feb 26, 2016 at 02:45:38PM -0700, Jeff Law wrote: > >2016-02-26 Jakub Jelinek > > > > PR c/69796 > > PR c/69974 > > * c-parser.c (c_parser_translation_unit): Don't change TREE_TYPE > > of incomplete decls to error_mark_node. > > > > *

Re: [PATCH][AArch64] PR target/69613: Return zero TARGET_SHIFT_TRUNCATION_MASK when SHIFT_COUNT_TRUNCATED is false

On Fri, Feb 26, 2016 at 1:44 PM, H.J. Lu wrote: > On Fri, Feb 26, 2016 at 7:50 AM, James Greenhalgh > wrote: >> On Thu, Feb 25, 2016 at 09:25:45AM +, Kyrill Tkachov wrote: >>> Hi all, >>> >>> In this wrong-code PR we get bad code when

Re: [PATCH, rs6000] Fixing PR 67145

On Fri, Feb 26, 2016 at 01:35:10PM -0800, Richard Henderson wrote: > On 02/26/2016 01:03 PM, Segher Boessenkool wrote: > > On Thu, Feb 25, 2016 at 09:08:32PM -0800, Richard Henderson wrote: > >> + /* Perform rematerialization if only all operands are registers and > >> + all

Re: [C PATCH] Fix C error-recovery (PR c/69796, PR c/69974)

On 02/26/2016 07:43 AM, Jakub Jelinek wrote: Hi! Already PR69483 and these two further PRs show that it is really a bad idea to set TREE_TYPE of decls with incomplete types to error_mark_node, there are lots of places in the middle-end that don't expect error_mark_nodes appearing so late. I've

Re: [PATCH][AArch64] PR target/69613: Return zero TARGET_SHIFT_TRUNCATION_MASK when SHIFT_COUNT_TRUNCATED is false

On Fri, Feb 26, 2016 at 7:50 AM, James Greenhalgh wrote: > On Thu, Feb 25, 2016 at 09:25:45AM +, Kyrill Tkachov wrote: >> Hi all, >> >> In this wrong-code PR we get bad code when synthesising a TImode right shift >> by variable amount using DImode shifts during

Re: [PATCH] Fix up recent texinfo regression

On 02/26/2016 01:55 PM, Jakub Jelinek wrote: On Fri, Feb 26, 2016 at 01:09:57PM -0700, Martin Sebor wrote: On 02/26/2016 12:51 PM, Jakub Jelinek wrote: I've noticed today: ../../gcc/doc/extend.texi:10717: warning: `.' or `,' must follow @xref, not A ../../gcc/doc/extend.texi:10764: warning:

Re: [PATCH, rs6000] Fixing PR 67145

On Fri, Feb 26, 2016 at 01:10:17PM -0800, Richard Henderson wrote: > On 02/26/2016 01:01 PM, Segher Boessenkool wrote: > >> How do you imagine the rs6000 change will regress codegen? > > > > Combine of sequences with double-length adds. > > What sort of test case are you imagining here? The

Re: [PATCH, rs6000] Fixing PR 67145

On 02/26/2016 01:03 PM, Segher Boessenkool wrote: > On Thu, Feb 25, 2016 at 09:08:32PM -0800, Richard Henderson wrote: >> + /* Perform rematerialization if only all operands are registers and >> + all operations are PLUS. */ >> + for (i = 0; i < n_ops; i++) >> +if

Re: [wwwdocs] Update -Wnonnull description

On Thu, 25 Feb 2016, Marek Polacek wrote: > Now that -Wnonnull-comare has been split out of -Wnonnull, we should > also update the porting_to text. Is this sufficient? It is for me. :-) Unless anyone else complains, go ahead and commit. Thanks, Gerald

Re: [PATCH] [wwwdocs] Add a "Plugin issues" section to the GCC 6 porting guide

Hi David, On Thu, 11 Feb 2016, David Malcolm wrote: > I've (mostly) ported gcc-python-plugin to gcc 6. The attached patch > for the gcc website starts a new "Plugin issues" section, and covers > the biggest issue I ran into (FWIW the suggested compatibility typedef > is the one I committed to

Re: [PATCH 2/4] Replace ENABLE_CHECKING macro with flag_checking in GNAT

On 02/24/2016 07:10 AM, marxin wrote: gcc/ada/ChangeLog: 2016-02-24 Martin Liska * gcc-interface/utils.c (set_reverse_storage_order_on_pad_type): Replace ENABLE_CHECKING macro with flag_checking. OK. jeff

Re: Revert gcc r227962

On 02/26/2016 04:04 AM, JonY wrote: Hi, I've submitted a patch that was committed as r227962, it causes some unintended side effects (namely libuuid on Cygwin). Can someone please revert? Kai still needs some time to setup his gcc development environment. We'd need to have a better sense of

Re: [PATCH, rs6000] Fixing PR 67145

On 02/26/2016 01:01 PM, Segher Boessenkool wrote: >> How do you imagine the rs6000 change will regress codegen? > > Combine of sequences with double-length adds. What sort of test case are you imagining here? The trivial tests I've looked at have all been optimal (before and after). > It

[PING^2] Re: [PATCH] [wwwdocs] Add a "Plugin issues" section to the GCC 6 porting guide

Ping On Thu, 2016-02-18 at 10:44 -0500, David Malcolm wrote: > Ping: > https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00765.html > > > On Thu, 2016-02-11 at 10:12 -0500, David Malcolm wrote: > > I've (mostly) ported gcc-python-plugin to gcc 6. The attached > > patch > > for the gcc website

Re: [PATCH, rs6000] Fixing PR 67145

On Thu, Feb 25, 2016 at 09:08:32PM -0800, Richard Henderson wrote: > diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c > index 450fa8b..9d55e7b 100644 > --- a/gcc/simplify-rtx.c > +++ b/gcc/simplify-rtx.c > @@ -4421,9 +4421,17 @@ simplify_plus_minus (enum rtx_code code, machine_mode > mode,

Re: [PATCH, rs6000] Fixing PR 67145

On Fri, Feb 26, 2016 at 12:51:10PM -0800, Richard Henderson wrote: > > What is the rs6000 ICE? > > The simplify-rtx.c patch causes (reg:M ca) to get sorted to a different spot > in > the (plus (plus r1 r2) r3) chain than the rs6000 backend expects, producing an > ICE due to an unrecognizable

Re: [PATCH] Fix up recent texinfo regression

On Fri, Feb 26, 2016 at 01:09:57PM -0700, Martin Sebor wrote: > On 02/26/2016 12:51 PM, Jakub Jelinek wrote: > >I've noticed today: > >../../gcc/doc/extend.texi:10717: warning: `.' or `,' must follow @xref, not A > >../../gcc/doc/extend.texi:10764: warning: `.' or `,' must follow @xref, not A > >

Re: [PATCH, rs6000] Fixing PR 67145

On 02/26/2016 12:41 PM, Segher Boessenkool wrote: > On Thu, Feb 25, 2016 at 09:08:32PM -0800, Richard Henderson wrote: >> It's the simplify-rtx.c portion of the patch that fixes the i686 regression. >> >> In the PR, Alan raises some good points, but I don't believe that we can >> address those

Re: [PATCH, rs6000] Fixing PR 67145

On Thu, Feb 25, 2016 at 09:08:32PM -0800, Richard Henderson wrote: > It's the simplify-rtx.c portion of the patch that fixes the i686 regression. > > In the PR, Alan raises some good points, but I don't believe that we can > address those for gcc6. A new rtl reassoc optimization that takes loop

Re: [PATCH] Fix PR69760

On Wed, Feb 24, 2016 at 6:49 AM, Richard Biener wrote: > > The following fixes bogus SCEV analysis for expressions that are only > executed conditionally [note: conditionally here doesn't include > after a taken exit]. Basically we have to make sure further analysis > does not

Re: [PATCH] Fix up recent texinfo regression

On 02/26/2016 12:51 PM, Jakub Jelinek wrote: Hi! I've noticed today: ../../gcc/doc/extend.texi:10717: warning: `.' or `,' must follow @xref, not A ../../gcc/doc/extend.texi:10764: warning: `.' or `,' must follow @xref, not A After reading info texinfo on @xref and @pxref, I believe it is

Re: [PATCH] Fix "no-vsx" target attribute handling (PR target/69969)

On Fri, Feb 26, 2016 at 2:27 PM, Jakub Jelinek wrote: > Hi! > > Most of the errors and warnings in rs6000_option_override_internal > are emitted only if the particular option is explicit, e.g. > if (TARGET_P9_DFORM && !TARGET_P9_VECTOR) > { > if

C++ PATCH for c++/69958 (wrong sizeof...)

alias templates are supposed to be transparent, so when we see template using wrapped2 = list>; the size_for needs to be expanded into sizeof...(something). There is no way to write this "something" in C++, but it's simple enough to leave it as an

[PATCH] Fix up recent texinfo regression

Hi! I've noticed today: ../../gcc/doc/extend.texi:10717: warning: `.' or `,' must follow @xref, not A ../../gcc/doc/extend.texi:10764: warning: `.' or `,' must follow @xref, not A After reading info texinfo on @xref and @pxref, I believe it is invalid to use @xref this way, in the middle of a

Re: [hsa merge 08/10] HSAIL BRIG description header file

On Feb 26, 2016, at 10:58 AM, Martin Jambor wrote: > I have asked HSA foundation Thanks. > The license is going to be: > > The MIT License (MIT) Wonderful.

[PATCH] Fix "no-vsx" target attribute handling (PR target/69969)

Hi! Most of the errors and warnings in rs6000_option_override_internal are emitted only if the particular option is explicit, e.g. if (TARGET_P9_DFORM && !TARGET_P9_VECTOR) { if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) error ("-mpower9-dform requires

Re: [PATCH] powerpc: Handle DImode rotatert implemented with rlwinm (PR69946)

On Fri, Feb 26, 2016 at 1:52 PM, Segher Boessenkool wrote: > On Thu, Feb 25, 2016 at 10:52:29AM -0500, David Edelsohn wrote: >> Please add a short comment explaining why rs6000_insn_for_shift_mask >> doesn't need to match the logic in rs6000_is_valid_shift_mask >>

Re: [hsa merge 08/10] HSAIL BRIG description header file

Hi, I hope I've got some good news: On Thu, Jan 14, 2016 at 05:18:56PM -0800, Ian Lance Taylor wrote: > Jakub Jelinek writes: > > > On Wed, Jan 13, 2016 at 06:39:33PM +0100, Martin Jambor wrote: > >> the following patch adds a BRIG (binary representation of HSAIL) > >>

Re: [PATCH] powerpc: Handle DImode rotatert implemented with rlwinm (PR69946)

On Thu, Feb 25, 2016 at 10:52:29AM -0500, David Edelsohn wrote: > Please add a short comment explaining why rs6000_insn_for_shift_mask > doesn't need to match the logic in rs6000_is_valid_shift_mask > converting rotates to simple shifts. I added this comment: --- trunk/gcc/config/rs6000/rs6000.c

Re: (Non-)offloading diagnostics

Hi, On Fri, Feb 26, 2016 at 06:51:34PM +0100, Jakub Jelinek wrote: > On Fri, Feb 26, 2016 at 06:18:13PM +0100, Martin Jambor wrote: > > > I'm a proponent of enabling as many useful warnings by default, or if not > > > by default, then with -Wall. -Whsa is enabled by default, and has thus > > >

Re: Fix PR44281 (bad RA with global regs)

On 02/26/2016 08:41 AM, Bernd Schmidt wrote: On 02/22/2016 03:37 PM, Richard Biener wrote: Do calls properly clobber them even if they are not in the set of call-clobbered regs? Are asm()s properly using/clobbering them? I think you are allowed to use them in asm()s without adding constraints

Re: [Fortran, Patch] (Coarrays) Wrong events size

Dear Alessandro, Seconded! I saw your ping on my phone and was going to respond. well, now :-) Thanks for the patch Paul On 26 February 2016 at 18:29, Thomas Koenig wrote: > Hi Allessandro, > >> * PING * > > > Looks obvious and simple enough for me. > > OK. > >

Re: [Patch, Fortran] PR 69495: unused-label warning does not tell which flag triggered it

double-ping ... 2016-02-12 0:29 GMT+01:00 Janus Weil : > ping! > > 2016-02-05 19:19 GMT+01:00 Janus Weil : >> Hi all, >> >> I have slightly updated the patch now to avoid string-breaking issues >> (even if it may not be a problem at all, as mentioned by

Re: (Non-)offloading diagnostics

On Fri, Feb 26, 2016 at 06:18:13PM +0100, Martin Jambor wrote: > > I'm a proponent of enabling as many useful warnings by default, or if not > > by default, then with -Wall. -Whsa is enabled by default, and has thus > > set a precedent of doing that. > > I am not sure I'd go as far as "as many

Re: [PR 69920] Prevent SRA from leaving a removed SSA_NAME in IL

On February 26, 2016 5:15:43 PM GMT+01:00, Martin Jambor wrote: >Hi, > >my fix for PR 69666 has caused quite a few regressions accross the >borad where SRA removed a SSA_NAME which however still was in the IL >(and usually stumbled upon it itself straight away). > >The removal

libgo patch committed: Add some Getsockopt functions to the syscall package

This patch adds some Getsockopt functions to the syscall package. These functions exist in the master library, but never made it into gccgo's syscall package. This fixes GCC PR 69966. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index:

[PATCH] update include/plugin-api.h to add hooks for section alignment + size

Hello, I would like to update the gcc plugin API to include interfaces for querying section size and alignment. The intent is to make it easier for plugins to do link-time reordering of .bss/.data/.rodata sections to reduce padding and/or improve cache utilization. I've posted a patch to

Re: [Fortran, Patch] (Coarrays) Wrong events size

Hi Allessandro, * PING * Looks obvious and simple enough for me. OK. Thanks for the patch! Thomas

Re: (Non-)offloading diagnostics

Hi, On Fri, Feb 26, 2016 at 05:46:33PM +0100, Thomas Schwinge wrote: > Hi! > > In light of the -Whsa testsuite patches just posted, I think we first > need to clarify the general policy questions I posted a month ago: > > On Tue, 26 Jan 2016 11:46:14 +0100, I wrote: > > On Thu, 10 Dec 2015

Re: (Non-)offloading diagnostics

Hi! In light of the -Whsa testsuite patches just posted, I think we first need to clarify the general policy questions I posted a month ago: On Tue, 26 Jan 2016 11:46:14 +0100, I wrote: > On Thu, 10 Dec 2015 18:51:48 +0100, Martin Jambor wrote: > > On Mon, Dec 07, 2015 at

Re: [PATCH] Fix powerpc shift/rotate/mask insn handling (PR target/69946)

On Fri, Feb 26, 2016 at 11:02 AM, Jakub Jelinek wrote: > Hi! > > Segher has added last year a few routines for the shift/rotate + mask > patterns, insns always have one predicate which tests if PowerPC supports > such pattern, and another that emits the instruction for it. > >

[PR 69920] Prevent SRA from leaving a removed SSA_NAME in IL

Hi, my fix for PR 69666 has caused quite a few regressions accross the borad where SRA removed a SSA_NAME which however still was in the IL (and usually stumbled upon it itself straight away). The removal path should not be executed when there is an SSA_NAME on the LHS, the code clearly is not

Re: [PATCH 3/3] contrib/config-list.mk: Add aarch64-rtems and x86_64-rtems

On Thu, Feb 25, 2016 at 02:49:10PM -0600, Joel Sherrill wrote: > * contrib/config-list.mk: Add aarch64-rtems and x86_64-rtems The AArch64 part of this is OK. Thanks, James > --- > contrib/config-list.mk | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-)

Re: [PATCH 1/3] Add aarch64-*-rtems* target

On Thu, Feb 25, 2016 at 02:49:08PM -0600, Joel Sherrill wrote: > * gcc/config.gcc, libgcc/config.host: Add aarch64-*-rtems*. > * gcc/config/aarch64/rtems.h: New file. OK. Thanks, James > --- > gcc/config.gcc | 11 +-- > gcc/config/aarch64/rtems.h | 28

Re: [hsa,testsuite] Introduce offload_device_shared_as effective target

On Fri, Feb 26, 2016 at 04:59:42PM +0100, Martin Jambor wrote: > this patch has been written by Keith McDaniel when he was working at > AMD (and so it should be covered by their blanket copyright > assignment) and adds a libgomp testsuite effective target predicate > offload_device_shared_as that

Re: [hsa, testsuite] Suppress hsa warnings in libgomp tests

On Fri, Feb 26, 2016 at 04:59:57PM +0100, Martin Jambor wrote: > just like with the compiler gomp testsuite, we need to add -Wno-hsa to > options when compiling libgomp testcases in order not to have "excess > errors" failures when HSA is enabled. There are quite many of such > testcases on the

Re: [omp, hsa] Do not gridify simd constructs

On Fri, Feb 26, 2016 at 04:57:19PM +0100, Martin Jambor wrote: > unfortunately, I have missed two execution failures when using HSA > (teams-6.f90 and target1.f90), both of which are caused by not > handling the simd part of combined target teams distribute parallel > for simd construct. I have

[PATCH] Fix powerpc shift/rotate/mask insn handling (PR target/69946)

Hi! Segher has added last year a few routines for the shift/rotate + mask patterns, insns always have one predicate which tests if PowerPC supports such pattern, and another that emits the instruction for it. The testcase in the patch is miscompiled, we end up with an instruction with out of

[hsa,testsuite] New directory for HSA-specific C testcases

Hi, we would like a place to have some HSA-specific tests, which would only run not only when HSA is enabled at configuration time but also when HSA hardware is present and used for offloading. The only way to detect that situation I could think of is to run a simple kernel with environment

[hsa,testsuite] Adjust libgomp tests that do not work on host fallback

Hi, this patch avoids run-time failures in libgomp testsuite that curtrently happen when HSA offloading is actually used. All of them currently require the offload_device effective target which the patch changes to offload_device_nonshared_as one. For some tests, such as

[hsa, testsuite] Suppress hsa warnings in libgomp tests

Hi, just like with the compiler gomp testsuite, we need to add -Wno-hsa to options when compiling libgomp testcases in order not to have "excess errors" failures when HSA is enabled. There are quite many of such testcases on the trunk because I have disabled the dynamic parallelism way of

[hsa, testsuite] Suppress hsa warnings in compiler gomp tests

Hi, compilation of (some) target constructs in the following testcases fails and the warning the compiler gives out by default are then reported as excess errors. There are two options how to deal with them. Either we can change the gomp.exp files to pass -Wno-hsa as the default set of options

[hsa,testsuite] Introduce offload_device_shared_as effective target

Hello, this patch has been written by Keith McDaniel when he was working at AMD (and so it should be covered by their blanket copyright assignment) and adds a libgomp testsuite effective target predicate offload_device_shared_as that allows us to run tests only when target constructs are run on a

[hsa, testsuite] Gridification tests

Hi, the patch below adds a DejaGNU effective target predicate (is that the correct dejagnu term?) offload_hsa so that selected tests can be run only if the hsa offloading is enabled. I hope it is fairly standard stuff. Additionally, it adds one C/C++ and one Fortran testsuite to check that

[hsa/69568] Fix ld instruction type for packed data

Hi, this is a fix for another type of HSA immediate operands that we got wrong. Apparently, the immediate value that is to be used in an operation on packed type must be unsigned (unless it is 128bit, then it has to be bit-typed, which is however something we are handling correctly even now).

[hsa/69674] Make testsuite libgomp.c/for-3.c compile with -m32

Hi, the following wrong decision about HSA pointer type leads to hitting an assert later in the out-of-ssa phase for 32bit targets. I have not attempted to test HSA on a 32bit i686 yet, I believe there is no functional runtime (although it should be possible to come up with one) and we do not

[hsa] Satisfy conditional move operand type constrains

Hi, It turned out that we got the types of conditional move operands and their immediate operands wrong in, partly because we missed a detail in the specs, partly because the finalizer/verifier is even stricter in one aspect. I'll commit the bootstrapped and tested fix below shortly. Thanks,

[hsa] Fail in presence of atomic operations in private segment

Hi, the HSA does not allow atomic instructions operating on the private segment because they are quite pointless. In the long term, we should put addressable local variables in the global memory somewhere (I'm going to look at the nvidia stack effort soon). But for now we need to fail in the

[omp, hsa] Do not gridify simd constructs

Hi, unfortunately, I have missed two execution failures when using HSA (teams-6.f90 and target1.f90), both of which are caused by not handling the simd part of combined target teams distribute parallel for simd construct. I have not really thought through how exactly should GPUs teat the simd

Re: [PATCH][AArch64] Set TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is the default node to recalculate optab availability

On Thu, Feb 25, 2016 at 11:04:21AM +, Kyrill Tkachov wrote: > Hi all, > > Seems like aarch64 is suffering from something similar to PR 69245 as well. > If a target pragma sets the target state to the same as the > target_option_default_node the node is just a pointer to >

Re: [PATCH][AArch64] PR target/69613: Return zero TARGET_SHIFT_TRUNCATION_MASK when SHIFT_COUNT_TRUNCATED is false

On Thu, Feb 25, 2016 at 09:25:45AM +, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR we get bad code when synthesising a TImode right shift > by variable amount using DImode shifts during expand. > > The expand_double_word_shift function expands two paths: one where the > variable

Re: [PATCH][AArch64] Remove an unused reload hook.

On Thu, Feb 25, 2016 at 12:00:58PM +0100, Yvan Roux wrote: > Hi, > > On 26 January 2015 at 18:01, Matthew Wahab wrote: > > Hello, > > > > The LEGITIMIZE_RELOAD_ADDRESS macro is only needed for reload. Since the > > Aarch64 backend no longer supports reload, this macro is

Re: Fix PR44281 (bad RA with global regs)

On 02/22/2016 03:37 PM, Richard Biener wrote: Do calls properly clobber them even if they are not in the set of call-clobbered regs? Are asm()s properly using/clobbering them? I think you are allowed to use them in asm()s without adding constraints for them? Calls do, asms currently don't

Re: Wonly-top-basic-asm

On 02/21/2016 11:27 AM, David Wohlferd wrote: So now what? I have one Bernd who likes the sample, and one who doesn't. Obviously I think what I'm proposing is better than what's there now and I've done my best to say why. But me believing it to be better doesn't get anything checked in. I

[PATCH] S/390: PR69709 Fix risbg splitter

This fixes a wrong code generation problem with the splitters introduced with that patch: https://gcc.gnu.org/ml/gcc-patches/2015-07/msg01840.html The target operand is used as temporary. This fails if it matches the source of the left shift which is read after writing the temporary. Thanks to

Re: [AArch64] Emit square root using the Newton series

On Mon, Feb 22, 2016 at 06:50:44PM -0600, Evandro Menezes wrote: > In preparation for the patch adding the Newton series also for > square root, I'd like to propose this patch changing the name of the > existing tuning flag for the reciprocal square root. This is fine, other names like sw_rsqrt,

Re: [PATCH 1/2][AArch64] Implement AAPCS64 updates for alignment attribute

On Mon, Feb 22, 2016 at 03:07:09PM +, Alan Lawrence wrote: > On 22/01/16 17:16, Alan Lawrence wrote: > > > >On 21/01/16 17:23, Alan Lawrence wrote: > >>On 18/01/16 17:10, Eric Botcazou wrote: > >>> > >>>Could you post the list of files that differ? How do they differ exactly? > >> > >>Hmmm.

Re: [PATCH][ARM][wwwdocs] Mention Cortex-A32 and Cortex-A35 support in changes.html for GCC 6

On 26/02/16 14:25, Kyrill Tkachov wrote: > Hi all, > > This patch adds a note to changes.html about the added support for > Cortex-A32 and Cortex-A35. > > Ok to commit? > OK. R. > Thanks, > Kyrill > > wwwdocs-a32-a35.patch > > > Index: htdocs/gcc-6/changes.html >

[C PATCH] Fix C error-recovery (PR c/69796, PR c/69974)

Hi! Already PR69483 and these two further PRs show that it is really a bad idea to set TREE_TYPE of decls with incomplete types to error_mark_node, there are lots of places in the middle-end that don't expect error_mark_nodes appearing so late. I've bootstrapped/regtested on x86_64-linux and

[PATCH] Fix PR69720

The following fixes PR69720 where with nested reductions that require unrolling the inner loop (and thus having multiple PHIs) we fail to properly build the reduction epilogue. Existing testcases in the testsuite are also affected but for them it doesn't matter as adding zero can be omitted

Re: [PATCH, rs6000] Fix PR61397 (test case update for P8 vector loads/stores)

On Fri, Feb 26, 2016 at 9:18 AM, Bill Schmidt wrote: > Hi, > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61397 was almost resolved a > year ago, but had a proposed patch by Mike Meissner that was never > vetted and committed. I've reviewed the patch and tested it

[PATCH][ARM][wwwdocs] Mention Cortex-A32 and Cortex-A35 support in changes.html for GCC 6

Hi all, This patch adds a note to changes.html about the added support for Cortex-A32 and Cortex-A35. Ok to commit? Thanks, Kyrill Index: htdocs/gcc-6/changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v

[PATCH, rs6000] Fix PR61397 (test case update for P8 vector loads/stores)

Hi, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61397 was almost resolved a year ago, but had a proposed patch by Mike Meissner that was never vetted and committed. I've reviewed the patch and tested it on GCC 5 and GCC 6, and with the patch applied we see the test pass for both 32-bit and

Re: [WWWDocs] Deprecate support for non-thumb ARM devices

On 24/02/16 13:59, Richard Earnshaw (lists) wrote: > After discussion with the ARM port maintainers we have decided that now > is probably the right time to deprecate support for versions of the ARM > Architecture prior to ARMv4t. This will allow us to clean up some of > the code base going

Re: [PATCH][LRA]Don't generate reload for output scratch operand from reload instruction.

Hi Richard, On 26/02/16 12:57, Richard Biener wrote: On Fri, Feb 26, 2016 at 1:54 PM, Renlin Li wrote: I have checked, x86, arm, aarch64, mips, arc all have such patterns. But it's not triggered. In my case, it's triggered by compiling glibc with local change.

Re: [PATCH][LRA]Don't generate reload for output scratch operand from reload instruction.

On Fri, Feb 26, 2016 at 1:54 PM, Renlin Li wrote: > Hi all, > > I admit that, the title looks a little bit confusing. > > The situation is like this, > To make insn_1 strict, lra generates a new insn_1_reload insn. > In insn_1_reload, there is a scratch operand with this

[PATCH][LRA]Don't generate reload for output scratch operand from reload instruction.

Hi all, I admit that, the title looks a little bit confusing. The situation is like this, To make insn_1 strict, lra generates a new insn_1_reload insn. In insn_1_reload, there is a scratch operand with this form clobber (match_scratch:MODE x "=") When lra tries to reload insn_1_reload in

Re: [PATCH] Fix up memset handling in DSE (PR rtl-optimization/69891)

On Fri, 26 Feb 2016, Jakub Jelinek wrote: > Hi! > > As analyzed by Eric, DSE mishandles memset calls if it can't figure out what > the arguments to memset exactly are (it handles only register arguments > right now), or if the second or third arguments are not CONST_INTs. > In that case we don't

Re: [PATCH][AArch64] Replace insn to zero up DF register

Evandro Menezes wrote: > > I have a question though: is it necessary to add the "fp" and "simd" > attributes to both movsf_aarch64 and movdf_aarch64 as well? You need at least the "simd" attribute, but providing "fp" as well is clearer (in principle the TARGET_FLOAT check

Re: [AArch64] Disable pcrelative_literal_loads with fix-cortex-a53-843419

Ping? On 26 January 2016 at 15:43, Christophe Lyon wrote: > With the attachment > > > On 26 January 2016 at 15:42, Christophe Lyon > wrote: >> Hi, >> >> This is a followup to PR63304. >> >> As discussed in bugzilla, this patch

Re: [PATCH, rs6000] Fixing PR 67145

On Fri, Feb 26, 2016 at 12:08 AM, Richard Henderson wrote: > It's the simplify-rtx.c portion of the patch that fixes the i686 regression. > > In the PR, Alan raises some good points, but I don't believe that we can > address those for gcc6. A new rtl reassoc optimization that

[PATCH] Fix up memset handling in DSE (PR rtl-optimization/69891)

Hi! As analyzed by Eric, DSE mishandles memset calls if it can't figure out what the arguments to memset exactly are (it handles only register arguments right now), or if the second or third arguments are not CONST_INTs. In that case we don't call record_store, because we don't know what to call

Re: [DOC,PATCH] Mention clog10, clog10f an clog10l in Builtins section.

On 02/26/2016 12:11 PM, Richard Biener wrote: > Ok with also addign them to the @findex list above. > > Richard. Thanks for review, updated version installed as r233738. Martin

Re: Avoid redundant DECL_ASSEMBLER_NAME computations for ODR types

On Fri, Feb 26, 2016 at 12:04 PM, Jakub Jelinek wrote: > On Fri, Feb 26, 2016 at 11:52:50AM +0100, Jan Hubicka wrote: >> Hi, >> while looking into the PR testcase I noticed that we detect wrong duplicate >> types. This is because we compute DECL_ASSEMBLER_NAME of a type variant

Re: Clear visibility of TYPE_DECL

On Fri, 26 Feb 2016, Jan Hubicka wrote: > Hi, > while looking into PR69589 I noticed that types are not merged when pragma > visibility does not match. This is because C++ FE stores visibility into > TYPE_DECL > that is used by FE only. This patch clears the flag in free_lang_data. > >

Re: [DOC,PATCH] Mention clog10, clog10f an clog10l in Builtins section.

On Fri, Feb 26, 2016 at 11:05 AM, Martin Liška wrote: > On 12/04/2015 10:45 AM, Martin Liška wrote: >> Hello. >> >> I noticed that Builtins section of documentation does not mention >> clog10{,f,l} functions. >> I've tried to write a patch, however I'm not sure how should be

Re: [PATCH] [RFA] [PR tree-optmization/69740] Schedule loop fixups when needed

On Fri, Feb 26, 2016 at 8:50 AM, Jeff Law wrote: > On 02/25/2016 03:00 AM, Richard Biener wrote: >> >> >> So I fail to see how only successor edges are relevant. Isn't the >> important >> case to catch whether we remove an edge marked EDGE_IRREDUCIBLE_LOOP? >> Even if the BB

Re: [RFC][PATCH][PR63586] Convert x+x+x+x into 4*x

On Fri, Feb 26, 2016 at 4:02 AM, kugan wrote: > > > Hi, > > This is an attempt to fix missed optimization: x+x+x+x -> 4*x as reported in > PR63586. > > Regression tested and bootstrapped on x86-64-linux-gnu with no new > regressions. > > Is this OK for next

Revert gcc r227962

Hi, I've submitted a patch that was committed as r227962, it causes some unintended side effects (namely libuuid on Cygwin). Can someone please revert? Kai still needs some time to setup his gcc development environment. Thanks. signature.asc Description: OpenPGP digital signature

Re: Avoid redundant DECL_ASSEMBLER_NAME computations for ODR types

On Fri, Feb 26, 2016 at 11:52:50AM +0100, Jan Hubicka wrote: > Hi, > while looking into the PR testcase I noticed that we detect wrong duplicate > types. This is because we compute DECL_ASSEMBLER_NAME of a type variant which > is not necessary. > > Bootstrapped/regested x86_64-linux and I checked

Re: [RFC][PATCH][PR40921] Convert x + (-y * z * z) into x - y * z * z

On Fri, Feb 26, 2016 at 4:02 AM, kugan wrote: > > > Hi, > > This is an attempt to fix missed optimization: x + (-y * z * z) => x - y * z > * z as reported in PR40921. > > Regression tested and bootstrapped on x86-64-linux-gnu with no new > regressions. > > Is

Avoid redundant DECL_ASSEMBLER_NAME computations for ODR types

Hi, while looking into the PR testcase I noticed that we detect wrong duplicate types. This is because we compute DECL_ASSEMBLER_NAME of a type variant which is not necessary. Bootstrapped/regested x86_64-linux and I checked dumps of xalancbmk to verify that nothing changes in ODR type merging

Clear visibility of TYPE_DECL

Hi, while looking into PR69589 I noticed that types are not merged when pragma visibility does not match. This is because C++ FE stores visibility into TYPE_DECL that is used by FE only. This patch clears the flag in free_lang_data. Bootstrapped/regtested x86_64-linux and tested it makes no

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