Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

On 04/07/17 15:38, Daniel Cederman wrote: On 2017-06-30 07:11, Sebastian Huber wrote: On 29/06/17 18:05, David Miller wrote: From: Daniel Cederman Date: Thu, 29 Jun 2017 17:15:43 +0200 I'm not thrilled with this, it's undocumented, the other workaround don't have

Re: [Patch, fortran] PR34640 - ICE when assigning item of a derived-component to a pointer

Hi Paul, first, this patch looks really good - it certainly fixes a lot of the ICEs. I have a few points (a part already mentioned in private mail). Consider the test case: module x use iso_c_binding implicit none type foo complex :: c integer :: i end type foo contains

[PATCH, i386]: Fix PR 81300, -fpeephole2 breaks __builtin_ia32_sbb_u64, _subborrow_u64 on AMD64

Hello! Attached patch tightens peephole2 condition to prevent unwanted flags_reg clobbering by insn patterns, emitted by ix86_expand_clear. 2017-07-04 Uros Bizjak PR target/81300 * config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes): Require dead

Re: [PATCH, i386] Fix PR 81294, _subborrow_u64 argument order inconsistent with intrinsic reference

On Tue, Jul 04, 2017 at 10:41:26PM +0200, Uros Bizjak wrote: > Hello! > > Apparently, Intel changed operand order with the new intrinsic > reference release version. Attached patch updates gcc intrinsic > headers accordingly. > > 2017-07-04 Uros Bizjak > > PR

[PATCH, i386] Fix PR 81294, _subborrow_u64 argument order inconsistent with intrinsic reference

Hello! Apparently, Intel changed operand order with the new intrinsic reference release version. Attached patch updates gcc intrinsic headers accordingly. 2017-07-04 Uros Bizjak PR target/81294 * config/i386/adxintrin.h (_subborrow_u32): Swap _X and _Y

Re: [patch,avr] Add support for devices with flash accessible by LD.

Georg-Johann Lay writes: > Hi, > > This patch adds support for devices that can access flash memory > by LD* instructions, hence there is no need to put .rodata in RAM. > > The default linker script for the new multilib versions already > supports this feature, it's similar to

Re: [PATHC][x86] Scalar mask and round RTL templates

Hello Sebastian, On 23 Jun 09:00, Peryt, Sebastian wrote: > Hi, > > This patch adds three extra RTL meta-templates for scalar round and mask. > Additionally fixes errors caused by previous mask and round usage in some of > the intrinsics that I found. Could you pls point which intrinsics did

Re: [PATCH] [AArch64] Fix PR71112

On Wed, Nov 23, 2016 at 5:25 AM, Hurugalawadi, Naveen wrote: > Hi, > > Please find attached the patch that fixes PR71112. > > The current implementation that handles SYMBOL_SMALL_GOT_28K in > aarch64_load_symref_appropriately access the high part of RTX for

Re: [PATCH][AArch64] Fix ILP32 memory access

On Tue, Jul 4, 2017 at 2:53 PM, Michael Matz wrote: > Hi, > > On Tue, 4 Jul 2017, Wilco Dijkstra wrote: > >> > You'll probably also have to set GNATBIND and GNATMAKE to the >> > appropriately suffixed variants. Just saying, because that's what I'm >> > usually forgetting and end up

Re: [PATCH GCC][2/2]Refine CFG and bound information for split loops

On Fri, Jun 30, 2017 at 5:09 PM, Jeff Law wrote: > On 06/14/2017 07:08 AM, Bin Cheng wrote: >> Hi, >> Loop split currently generates below control flow graph for split loops: >> + >> + .-- guard1 --. >> + v v >> +

Re: [PATCH GCC8][33/33]Fix PR69710/PR68030 by reassociate vect base address and a simple CSE pass

On Mon, Jul 3, 2017 at 5:12 PM, Jeff Law wrote: > On 04/18/2017 04:54 AM, Bin Cheng wrote: >> Hi, >> This is the same patch posted at >> https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02000.html, >> after rebase against this patch series. This patch was blocked because >>

Re: [PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

On 07/04/2017 06:41 AM, Jakub Jelinek wrote: > On Tue, Jul 04, 2017 at 02:00:13PM +0200, Richard Biener wrote: >>> That was intentional. If a->e != NULL, then we know that b->e != NULL, >>> because we have >>> else if (a->e != NULL && b->e == NULL) >>> return -1; >>> earlier. Similarly, if

Re: [PATCH][AArch64] Fix strict aliasing issue in gcc.target/aarch64/simd/vminmaxnm_1.c

On 04/07/17 15:39, Kyrill Tkachov wrote: > Hi all, > > While doing some unrelated work the > gcc.target/aarch64/simd/vminmaxnm_1.c testcase started failing for me. > Upon investigation it turns out that it breaks the C strict aliasing > rules in the CHECK macro by casting > a pointer to an

[PATCH][arm] Move some generated files out of the source tree

When I originally started work on the new options framework for ARM I'd worked on the assumption that AWK might not be available on every build machine (only on developer's machines). However, looking again I notice that all the options framework relies on it being present for every build. This

[PATCH][AArch64] Fix strict aliasing issue in gcc.target/aarch64/simd/vminmaxnm_1.c

Hi all, While doing some unrelated work the gcc.target/aarch64/simd/vminmaxnm_1.c testcase started failing for me. Upon investigation it turns out that it breaks the C strict aliasing rules in the CHECK macro by casting a pointer to an incompatible type and dereferencing it. GCC even warns

Re: [PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

On July 4, 2017 2:41:52 PM GMT+02:00, Jakub Jelinek wrote: >On Tue, Jul 04, 2017 at 02:00:13PM +0200, Richard Biener wrote: >> > That was intentional. If a->e != NULL, then we know that b->e != >NULL, >> > because we have >> > else if (a->e != NULL && b->e == NULL) >> >

Re: [PATCH][AArch64] Fix ILP32 memory access

On Jul 04 2017, Wilco Dijkstra wrote: > Configure seems to be able to find gnatbind/gnatmake as they are in /usr/bin. Strange there are ada tools, but no ada compiler. Are you sure you installed all relevant ada packages? Andreas. -- Andreas Schwab,

Re: Profile upating in simd_clone_adjust

On Tue, Jul 04, 2017 at 03:46:26PM +0200, Jan Hubicka wrote: > Hi, > this is the last occurence of missing probability update during x86-64 > bootstrap I am not sure what is really going on here, > is haing probability as almost never executed OK? This is for the test whether the particular

Re: [PATCH 1/3, GCC/ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8

On 29/06/17 14:55, Thomas Preudhomme wrote: Hi, The driver is missing MIDR information for processors ARM Cortex-R7 and Cortex-R8 to support -march/-mcpu/-mtune=native on the command line. This patch adds the missing information. ChangeLog entry is as follows: *** gcc/ChangeLog ***

Re: [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8

Ping? Best regards, Thomas On 29/06/17 14:55, Thomas Preudhomme wrote: Hi, The driver is missing MIDR information for processors ARM Cortex-R7 and Cortex-R8 to support -march/-mcpu/-mtune=native on the command line. This patch adds the missing information. ChangeLog entry is as follows:

Re: [PATCH][AArch64] Fix ILP32 memory access

Hi, On Tue, 4 Jul 2017, Wilco Dijkstra wrote: > > You'll probably also have to set GNATBIND and GNATMAKE to the > > appropriately suffixed variants.  Just saying, because that's what I'm > > usually forgetting and end up with strange errors :) > > Configure seems to be able to find

Re: Profile upating in simd_clone_adjust

Jan Hubicka writes: > Hi, > this is the last occurence of missing probability update during x86-64 > bootstrap I am not sure what is really going on here, > is haing probability as almost never executed OK? > > Honza > > Index: omp-simd-clone.c >

Profile upating in simd_clone_adjust

Hi, this is the last occurence of missing probability update during x86-64 bootstrap I am not sure what is really going on here, is haing probability as almost never executed OK? Honza Index: omp-simd-clone.c === ---

Re: [PATCH][AArch64] Fix ILP32 memory access

Michael Matz wrote: > > You'll probably also have to set GNATBIND and GNATMAKE to the > appropriately suffixed variants.  Just saying, because that's what I'm > usually forgetting and end up with strange errors :) Configure seems to be able to find gnatbind/gnatmake as they are in /usr/bin.

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

On 2017-06-30 07:11, Sebastian Huber wrote: On 29/06/17 18:05, David Miller wrote: From: Daniel Cederman Date: Thu, 29 Jun 2017 17:15:43 +0200 I'm not thrilled with this, it's undocumented, the other workaround don't have it and I don't think that we really need it.

Re: [PATCH][AArch64] Fix ILP32 memory access

Hi, On Tue, 4 Jul 2017, Ramana Radhakrishnan wrote: > Yeah it turns out that on the machine Wilco was using, we are running > 14.04 which has a gcc 4.8 base compiler that didn't have Ada on for > AArch64. > > I think we can work around by installing a gcc-5 package and then > setting CC to

Re: [PATCH v9] add -fpatchable-function-entry=N,M option

On Tue, Jul 04, 2017 at 02:27:00PM +0100, Richard Earnshaw (lists) wrote: > > > > How about omitting the recording step and document that? This way the > > instrumentation can still be useful on e.g. a.out format; the framework > > would then have to check around each function entry whether the

Re: [PATCH v9] add -fpatchable-function-entry=N,M option

Hi, On Tue, 4 Jul 2017, Michael Matz wrote: > I don't think so: get_insn_template() should always return strings in > .rodata, even for output statements, and should never point into GC > memory. Bah, ignore that. I should refetch mail before answering mid-thread ;) Ciao, Michael.

Re: [PATCH v9] add -fpatchable-function-entry=N,M option

Hello Richard, On Tue, 4 Jul 2017, Richard Earnshaw (lists) wrote: > > +void > > +default_print_patchable_function_entry (FILE *file, > > + unsigned HOST_WIDE_INT patch_area_size, > > + bool record_p) > > +{ > > + static const

Re: [PATCH v9] add -fpatchable-function-entry=N,M option

On 04/07/17 14:14, Torsten Duwe wrote: > On Tue, Jul 04, 2017 at 12:02:47PM +0100, Richard Earnshaw (lists) wrote: >> On 13/06/17 18:00, Torsten Duwe wrote: >>> Changes since v8: >>> >>> * Documentation changes as requested by Sandra >>> * 3 functional test cases added >>> >>> Torsten >>>

Fix ChangeLog format in r247584

Hi, This patch fixes relative pathnames in gcc/ChangeLog for r247584. Committed as obvious to trunk, GCC 5, 6 and 7. Best regards, Thomas diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f9e00198bbfd352960685b5c72193570e232e68a..39bdcb12ebbad3cdbdce6b9d4dd87c28610e37fe 100644 ---

Re: [PATCH v9] add -fpatchable-function-entry=N,M option

On Tue, Jul 04, 2017 at 12:02:47PM +0100, Richard Earnshaw (lists) wrote: > On 13/06/17 18:00, Torsten Duwe wrote: > > Changes since v8: > > > > * Documentation changes as requested by Sandra > > * 3 functional test cases added > > > > Torsten > > > > > > gcc/c-family/ChangeLog > >

Re: [PATCH][AArch64] Fix ILP32 memory access

On Tue, Jul 4, 2017 at 1:56 PM, Arnaud Charlet wrote: > On Tue, Jul 04, 2017 at 12:19:35PM +, Wilco Dijkstra wrote: >> Andreas Schwab wrote: >> > @@ -5207,6 +5209,7 @@ aarch64_print_operand (FILE *f, rtx x, int code) >> > >> >case MEM: >> > output_address

Re: [PATCH][AArch64] Fix ILP32 memory access

On Tue, Jul 04, 2017 at 12:19:35PM +, Wilco Dijkstra wrote: > Andreas Schwab wrote: > > @@ -5207,6 +5209,7 @@ aarch64_print_operand (FILE *f, rtx x, int code) > >  > >    case MEM: > >  output_address (GET_MODE (x), XEXP (x, 0)); > > +   gcc_assert (GET_MODE (XEXP (x, 0)) ==

Re: [PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

On Tue, Jul 04, 2017 at 02:00:13PM +0200, Richard Biener wrote: > > That was intentional. If a->e != NULL, then we know that b->e != NULL, > > because we have > > else if (a->e != NULL && b->e == NULL) > > return -1; > > earlier. Similarly, if a->e == NULL, then we know that b-> == NULL,

Re: [Patch ARM] Add initial tuning for Cortex-A55 and Cortex-A75

On 04/07/17 12:28, James Greenhalgh wrote: > > Much like my AArch64 patch a few weeks ago, this patch adds support > for the ARM Cortex-A75 and Cortex-A55 processors through the > -mcpu/-mtune values cortex-a55 and cortex-a75, and an > ARM DynamIQ big.LITTLE configuration of these two processors

Re: [PATCH GCC][3/4]Generalize dead store elimination (or store motion) across loop iterations in predcom

On Tue, Jul 4, 2017 at 2:06 PM, Bin.Cheng wrote: > On Tue, Jul 4, 2017 at 12:19 PM, Richard Biener > wrote: >> On Mon, Jul 3, 2017 at 4:17 PM, Bin.Cheng wrote: >>> On Mon, Jul 3, 2017 at 10:38 AM, Richard Biener >>>

Re: [PATCH][AArch64] Fix ILP32 memory access

On Jul 04 2017, Wilco Dijkstra wrote: > checking whether compiler driver understands Ada... no You need to fix that first. Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something

Re: [7/7] Pool alignment information for common bases

On Tue, Jul 4, 2017 at 2:01 PM, Richard Sandiford wrote: > Richard Biener writes: >> On Mon, Jul 3, 2017 at 9:49 AM, Richard Sandiford >> wrote: >>> @@ -2070,8 +2143,7 @@ vect_find_same_alignment_drs (struct

Re: [PATCH][AArch64] Fix ILP32 memory access

Andreas Schwab wrote: > @@ -5207,6 +5209,7 @@ aarch64_print_operand (FILE *f, rtx x, int code) >  >    case MEM: >  output_address (GET_MODE (x), XEXP (x, 0)); > +   gcc_assert (GET_MODE (XEXP (x, 0)) == Pmode); >  break; >  >    case CONST: > That breaks a lot of

Re: C PATCH to fix ICE-on-invalid with __atomic_load (PR c/81231)

On Tue, 4 Jul 2017, Marek Polacek wrote: > This patch fixes an ICE-on-invalid with __atomic_*. We should check > that we're dealing with a complete type before we're accessing its > TYPE_SIZE_UNIT. > > Bootstrapped/regtested on x86_64-linux, ok for trunk? OK. -- Joseph S. Myers

Re: [PATCH GCC][3/4]Generalize dead store elimination (or store motion) across loop iterations in predcom

On Tue, Jul 4, 2017 at 12:19 PM, Richard Biener wrote: > On Mon, Jul 3, 2017 at 4:17 PM, Bin.Cheng wrote: >> On Mon, Jul 3, 2017 at 10:38 AM, Richard Biener >> wrote: >>> On Tue, Jun 27, 2017 at 12:49 PM, Bin Cheng

Re: [7/7] Pool alignment information for common bases

Richard Biener writes: > On Mon, Jul 3, 2017 at 9:49 AM, Richard Sandiford > wrote: >> @@ -2070,8 +2143,7 @@ vect_find_same_alignment_drs (struct dat >>if (dra == drb) >> return; >> >> - if (!operand_equal_p (DR_BASE_OBJECT

Re: [PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

On Tue, 4 Jul 2017, Jakub Jelinek wrote: > On Tue, Jul 04, 2017 at 01:46:25PM +0200, Richard Biener wrote: > > > 2017-07-04 Jakub Jelinek > > > > > > PR debug/81278 > > > * tree-vrp.c (compare_assert_loc): Only test if a->e is NULL, > > > !a->e == !b->e has been

Re: [PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

On Tue, Jul 04, 2017 at 01:46:25PM +0200, Richard Biener wrote: > > 2017-07-04 Jakub Jelinek > > > > PR debug/81278 > > * tree-vrp.c (compare_assert_loc): Only test if a->e is NULL, > > !a->e == !b->e has been verified already. Use e == NULL or > > e != NULL

Re: [PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

On Tue, 4 Jul 2017, Jakub Jelinek wrote: > Hi! > > The compare_assert_loc added recently to sort assert exprs that could > operand_equal_p the expressions/values in there unfortunately broke > -fcompare-debug. The problem is that DECL_UIDs don't have to be the same > between -g and -g0, and

Re: [PATCH] Fix bootstrap with brig FE

On Tue, 4 Jul 2017, Jakub Jelinek wrote: > Hi! > > Seems tree-cfg.h now requires profile-count.h (or some header that includes > it like basic-block.h) to be included first (the flattened headers without > including their dependencies and without aggregate headers are really terrible > idea), so

C PATCH to fix ICE-on-invalid with __atomic_load (PR c/81231)

This patch fixes an ICE-on-invalid with __atomic_*. We should check that we're dealing with a complete type before we're accessing its TYPE_SIZE_UNIT. Bootstrapped/regtested on x86_64-linux, ok for trunk? 2017-07-04 Marek Polacek PR c/81231 * c-common.c

Re: PR 81292: ICE on related strlens after r249880

On Tue, Jul 04, 2017 at 12:14:48PM +0100, Richard Sandiford wrote: > r249880 installed the result of a strlen in a strinfo if the strinfo > wasn't previously a full string. But as Jakub says in the PR comments, > we can't just do that in isolation, because there are no vdefs on the > call that

[PATCH] Fix bootstrap with brig FE

Hi! Seems tree-cfg.h now requires profile-count.h (or some header that includes it like basic-block.h) to be included first (the flattened headers without including their dependencies and without aggregate headers are really terrible idea), so right now bootstrap fails in brig FE. Fixed thusly,

[RFC] Add -fmap-abort-to-trap

Hi, In gcc we map __builtin_trap to abort if there's no trap insn: ... Built-in Function: void __builtin_trap (void) This function causes the program to exit abnormally. GCC implements this function by using a target-dependent mechanism (such as intentionally executing an illegal

[PATCH] Fix -fcompare-debug issues caused by recent VRP assert expr sorting changes (PR debug/81278)

Hi! The compare_assert_loc added recently to sort assert exprs that could operand_equal_p the expressions/values in there unfortunately broke -fcompare-debug. The problem is that DECL_UIDs don't have to be the same between -g and -g0, and thus what iterative_hash_expr returns might not be the

Re: [7/7] Pool alignment information for common bases

On Mon, Jul 3, 2017 at 9:49 AM, Richard Sandiford wrote: > This patch is a follow-on to the fix for PR81136. The testcase for that > PR shows that we can (correctly) calculate different base alignments > for two data_references but still tell that their

[Patch ARM] Add initial tuning for Cortex-A55 and Cortex-A75

Much like my AArch64 patch a few weeks ago, this patch adds support for the ARM Cortex-A75 and Cortex-A55 processors through the -mcpu/-mtune values cortex-a55 and cortex-a75, and an ARM DynamIQ big.LITTLE configuration of these two processors through the -mcpu/-mtune value cortex-a75.cortex-a55

Re: Update profile for haifa-sched's recovery blocks

> On Tue, 4 Jul 2017, Jan Hubicka wrote: > > > Hi, > > this is another bug I noticed while looking into Itanium rgression. > > There is no profile attached to recovery blocks in scheduler. > > I made them very unlikely, but I wonder if we can do better? After all > > we probably know the

Re: [PATCH GCC][3/4]Generalize dead store elimination (or store motion) across loop iterations in predcom

On Mon, Jul 3, 2017 at 4:17 PM, Bin.Cheng wrote: > On Mon, Jul 3, 2017 at 10:38 AM, Richard Biener > wrote: >> On Tue, Jun 27, 2017 at 12:49 PM, Bin Cheng wrote: >>> Hi, >>> For the moment, tree-predcom.c only supports >>>

Re: Update profile for haifa-sched's recovery blocks

On Tue, 4 Jul 2017, Jan Hubicka wrote: > Hi, > this is another bug I noticed while looking into Itanium rgression. > There is no profile attached to recovery blocks in scheduler. > I made them very unlikely, but I wonder if we can do better? After all > we probably know the probability of path

PR 81292: ICE on related strlens after r249880

r249880 installed the result of a strlen in a strinfo if the strinfo wasn't previously a full string. But as Jakub says in the PR comments, we can't just do that in isolation, because there are no vdefs on the call that would invalidate any related strinfos. This patch updates the related

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

Hi, Thanks for the review and comments on the patch. >> The proposed patch handled both the same.  This means the pattern >> shouldn't use range-info but instead match a more complex The patch handles as per the discussion by matching the pattern in match.pd. Bootstrapped and Regression tested

Re: [PATCH][1/2] Early LTO debug, simple-object part

On Tue, 20 Jun 2017, Richard Biener wrote: > On Wed, 7 Jun 2017, Richard Biener wrote: > > > On Fri, 19 May 2017, Richard Biener wrote: > > > > > > > > This is a repost (unchanged) of the simple-object ELF support for > > > early LTO debug transfer from IL object to a separate debug-only

Re: [PATCH][2/2] early LTO debug, main part

On Tue, 20 Jun 2017, Richard Biener wrote: > On Wed, 7 Jun 2017, Richard Biener wrote: > > > On Fri, 19 May 2017, Richard Biener wrote: > > > > > > > > This is a repost of the main part of the early LTO debug support. > > > The only changes relative to the last post is in the dwarf2out.c > > >

Re: [PATCH v9] add -fpatchable-function-entry=N,M option

On 13/06/17 18:00, Torsten Duwe wrote: > Changes since v8: > > * Documentation changes as requested by Sandra > * 3 functional test cases added > > Torsten > > > gcc/c-family/ChangeLog > 2017-06-13 Torsten Duwe > > * c-attribs.c (c_common_attribute_table): Add

Re: [PATCH] Enable addressable params sanitization with --param asan-stack=1.

On 07/04/2017 09:59 AM, Jakub Jelinek wrote: > On Tue, Jul 04, 2017 at 09:47:29AM +0200, Martin Liška wrote: >> As mentioned in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81040#c15, the >> sanitization is >> done only when one uses use-after-scope. That's caused by fact that I >> decorated the

[PATCH][OBVIOUS] Use xstrdup_for_dump in ipa-inline.c (PR ipa/81293).

Hello. It's obvious patch for case where we call cxx_printable_name_internal twice. Once a function name is found in buffer in a slot that then release for purpose of the second function name buffering. Installed as obvious. Martin gcc/ChangeLog: 2017-07-04 Martin Liska

[PATCH, 3/3] Handle GOMP_NVPTX_JIT={-O[0-4],-ori,-arch=} in libgomp nvptx plugin

On 07/04/2017 12:05 PM, Tom de Vries wrote: On 07/03/2017 04:24 PM, Tom de Vries wrote: On 07/03/2017 04:08 PM, Thomas Schwinge wrote: Hi! On Mon, 26 Jun 2017 17:29:11 +0200, Jakub Jelinek wrote: On Mon, Jun 26, 2017 at 03:26:57PM +, Joseph Myers wrote: On Mon, 26

Update profile for haifa-sched's recovery blocks

Hi, this is another bug I noticed while looking into Itanium rgression. There is no profile attached to recovery blocks in scheduler. I made them very unlikely, but I wonder if we can do better? After all we probably know the probability of path that will lead for speculation to suceed? Honza

[PATCH, 2/3] Handle GOMP_NVPTX_PTXRW in libgomp nvptx plugin

On 07/04/2017 12:05 PM, Tom de Vries wrote: On 07/03/2017 04:24 PM, Tom de Vries wrote: On 07/03/2017 04:08 PM, Thomas Schwinge wrote: Hi! On Mon, 26 Jun 2017 17:29:11 +0200, Jakub Jelinek wrote: On Mon, Jun 26, 2017 at 03:26:57PM +, Joseph Myers wrote: On Mon, 26

Fix bb-reorder code size regression on Itanium

Hi, better_edge_p will always return false when best_prob is uninitialized. This patch makes it to chose first edge with initialized probability instead. This solves code size regression seen on our Itanium tester at least for gzip's deflate. Will commit it after bootstrapping/regtesting

[PATCH, 1/3] Handle GOMP_NVPTX_{DISASM,SAVE_TEMPS} in libgomp nvptx plugin

On 07/04/2017 12:05 PM, Tom de Vries wrote: On 07/03/2017 04:24 PM, Tom de Vries wrote: On 07/03/2017 04:08 PM, Thomas Schwinge wrote: Hi! On Mon, 26 Jun 2017 17:29:11 +0200, Jakub Jelinek wrote: On Mon, Jun 26, 2017 at 03:26:57PM +, Joseph Myers wrote: On Mon, 26

Re: [PATCH, 2/4] Handle GOMP_OPENACC_NVPTX_{DISASM,SAVE_TEMPS} in libgomp nvptx plugin

On 07/03/2017 04:24 PM, Tom de Vries wrote: On 07/03/2017 04:08 PM, Thomas Schwinge wrote: Hi! On Mon, 26 Jun 2017 17:29:11 +0200, Jakub Jelinek wrote: On Mon, Jun 26, 2017 at 03:26:57PM +, Joseph Myers wrote: On Mon, 26 Jun 2017, Tom de Vries wrote: 2. Handle

Re: Handle data dependence relations with different bases

[Sorry for missing the previous messages] > Thanks. Just been retesting, and I think I must have forgotten > to include Ada last time. It turns out that the patch causes a dg-scan > regression in gnat.dg/vect17.adb, because we now think that if the > array RECORD_TYPEs *do* alias in: > >

Re: [PATCH] warn on mem calls modifying objects of non-trivial types (PR 80560)

On 29/06/17 17:15, Jan Hubicka wrote: > Hello, >> diff --git a/gcc/hash-table.h b/gcc/hash-table.h >> index 0f7e21a..443d16c 100644 >> --- a/gcc/hash-table.h >> +++ b/gcc/hash-table.h >> @@ -803,7 +803,10 @@ hash_table::empty_slow () >>m_size_prime_index = nindex; >>

Re: [RFC PATCH] -fsanitize=pointer-overflow support (PR sanitizer/80998)

On Tue, Jun 20, 2017 at 10:18:20AM +0200, Richard Biener wrote: > > Ok (of course, will handle this separately from the rest). > > Yes. Note I didn't look at the actual patch (yet). I'd like to ping the -fsanitize=pointer-overflow patch (though if you're busy, it can certainly wait a few

Re: [PATCH][testsuite] Add dg-require-stack-check

On 3 July 2017 at 17:30, Jeff Law wrote: > On 07/03/2017 09:00 AM, Christophe Lyon wrote: >> Hi, >> >> This is a follow-up to >> https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01791.html >> >> This patch adds dg-require-stack-check and updates the tests that use >> dg-options

Re: [PATCH] ASAN: handle addressable params (PR sanitize/81040).

On Fri, Jun 30, 2017 at 11:21:48AM +0200, Martin Liška wrote: > --- /dev/null > +++ b/gcc/testsuite/g++.dg/asan/function-argument-3.C > @@ -0,0 +1,27 @@ > +// { dg-do run } > +// { dg-shouldfail "asan" } > + > +typedef int v4si __attribute__ ((vector_size (16))); > + > +static __attribute__

Re: [PATCH 0/7] Support for the SPARC M8 cpu

Hi Jose, > This patch serie adds support for the SPARC M8 processor to GCC. > The SPARC M8 processor implements the Oracle SPARC Architecture 2017. [...] > Note that full binutils support for M8 was upstreamed in May 19. > Bootstrapped and tested in sparc64-linux-gnu. No regressions. since the

Re: Patch ping (Re: [PATCH] Fix PR81175, make gather builtins pure)

On Tue, 4 Jul 2017, Jakub Jelinek wrote: > Hi! > > On Tue, Jun 27, 2017 at 12:27:25PM +0200, Jakub Jelinek wrote: > > Fixed thusly, ok for trunk? Perhaps we should add another testcase to check > > similarly gatherpf builtin without the lhs, but we'd need different options. > > I'd like to

Re: Patch ping (Re: [PATCH] Fix PR81175, make gather builtins pure)

On Tue, Jul 4, 2017 at 10:35 AM, Jakub Jelinek wrote: > Hi! > > On Tue, Jun 27, 2017 at 12:27:25PM +0200, Jakub Jelinek wrote: >> Fixed thusly, ok for trunk? Perhaps we should add another testcase to check >> similarly gatherpf builtin without the lhs, but we'd need different

move cpu specific settings for VxWorks to cpu specific config file

Hello, This fixes an inaccuracy introduced in the recent series of patches preparing support for 64bit VxWorks configurations together with VxWorks 7. Alternative definitions for SIZE_TYPE, PTRDIFF_TYPE and RTP library options were provided through a common VxWorks configuration file, using

Patch ping (Re: [PATCH] Fix PR81175, make gather builtins pure)

Hi! On Tue, Jun 27, 2017 at 12:27:25PM +0200, Jakub Jelinek wrote: > Fixed thusly, ok for trunk? Perhaps we should add another testcase to check > similarly gatherpf builtin without the lhs, but we'd need different options. I'd like to ping this patch, ok for trunk? > 2017-06-27 Jakub Jelinek

Re: [PATCH] Enable addressable params sanitization with --param asan-stack=1.

On Tue, Jul 04, 2017 at 09:47:29AM +0200, Martin Liška wrote: > As mentioned in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81040#c15, the > sanitization is > done only when one uses use-after-scope. That's caused by fact that I > decorated the newly > created auto variables with

[PATCH] Enable addressable params sanitization with --param asan-stack=1.

Hello. As mentioned in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81040#c15, the sanitization is done only when one uses use-after-scope. That's caused by fact that I decorated the newly created auto variables with DECL_ARTIFICIAL = 1. Because of that static inline bool

Re: [PATCH] Fix removal of ifunc (PR ipa/81214).

On 07/03/2017 03:44 PM, Rainer Orth wrote: > Hi Martin, > >> Following patch fixes the issue where we do not emit ifunc and resolver >> for function that are not called in a compilation unit or and not >> referenced. >> >> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests.

Re: [PATCH] Save and restore EDGE_DFS_BACK in draw_cfg_edges

On Tue, 4 Jul 2017, Tom de Vries wrote: > [was: Re: [PATCH] Add dotfn ] > > On 07/03/2017 12:23 PM, Richard Biener wrote: > > > Btw, I think this needs fixing: > > > ... > > > /* Draw all edges in the CFG. Retreating edges are drawin as not > > > constraining, this makes the layout of the