On Thu, 7 Feb 2019, Rainer Orth wrote:
> Hi Honza,
>
> > PR ipa/88711
> > * gfortran.dg/pr79966.f90: Xfail for time being.
> > Index: ../../gcc/testsuite/gfortran.dg/pr79966.f90
> > ===
> > ---
Hi!
The following patch uses a simple data flow to find live (addressable)
variables at certain spots (for tail call discovery at the point of the
potential tail call, so that we don't reject tail calls because of variables
that can be known out of scope already so that people don't have to find
On Feb 7, 2019, Jason Merrill wrote:
> OK, that makes sense; it isn't always clear what the right handling of
> a USING_DECL is.
Indeed. Like, in shared_member_p, I'm wondering if we shouldn't recurse
if the USING_DECL maps to an overload, that IIUC might contain static
and non-static
On Feb 7, 2019, Jason Merrill wrote:
>> + PR c++/86322. */
> Wrong PR number.
Thanks
>> + if (local_specializations)
>> +if (tree r = retrieve_local_specialization (t))
>> + return r;
> Hmm, I would expect this to do the wrong thing for pack expansion of a
> lambda, giving us
On February 7, 2019 11:37:29 PM GMT+01:00, Jakub Jelinek
wrote:
>Hi!
>
>I've noticed pre_and_rev_post_order_compute_fn is one of (apparently
>many)
>functions that take a struct function * argument and accept any
>function, as
>long as it is cfun. For a patch I've been working on I actually
On 2/7/19 4:54 AM, Jonathan Wakely wrote:
On 23/12/18 21:27 -0500, Tom Honermann wrote:
Attached is a revised patch that addresses changes in P0482R6.
Changes from the prior patch include:
- Updated the value of the __cpp_char8_t feature test macro to 201811.
Tested on x86_64-linux.
There
On 2/7/19 4:44 AM, Jonathan Wakely wrote:
On 23/12/18 21:27 -0500, Tom Honermann wrote:
Attached is a revised patch that addresses changes in P0482R6.
Changes from the prior patch include:
- Updated the value of the __cpp_char8_t feature test macro to 201811.
Tested on x86_64-linux.
On 2/7/19 6:27 PM, Martin Sebor wrote:
On 2/7/19 4:00 PM, Jason Merrill wrote:
On 2/7/19 1:57 PM, Martin Sebor wrote:
+ /* The original numeric size as seen in the source code after
+ any substitution and before conversion to size_t. */
I don't think this should mention substitution.
Fixes lack of r30 save/restore on
// -m32 -fpic -ftls-model=initial-exec
__thread char* p;
char** f1 (void) { return }
and
// -m32 -fpic -msecure-plt
extern int foo (int);
int f1 (int x) { return foo (x); }
These are both caused by save_reg_p returning false when the pic
offset table reg (r30
Inline PLT calls need PLT to be an array of addresses. bss-plt works
differently.
Bootstrap and regression test on powerpc64-linux biarch in progress.
OK assuming no regressions?
* config/rs6000/rs6000.c (rs6000_longcall_ref): Don't use
inline plt for ABI_V4 bss-plt.
On Thu, 2019-01-31 at 08:46 +0100, Uros Bizjak wrote:
> On Wed, Jan 30, 2019 at 9:51 PM Janne Blomqvist
>
> > This seems to change the only user of support_fpu_trap() that is
> > different from support_fpu_flag(), so with this change one could
> > remove support_fpu_trap() entirely and modify all
> We'll need to add a copy of the LICENSE.TXT file to our sources, since
> it's referred to by the comments at the top of each PSTL file.
>
Right, we were going to discuss where the "right place" under
libstdc++-v3/ would be for that.
As for the rest, noted, I'll add them to the list for the
On 2/7/19 4:00 PM, Jason Merrill wrote:
On 2/7/19 1:57 PM, Martin Sebor wrote:
+ /* The original numeric size as seen in the source code after
+ any substitution and before conversion to size_t. */
I don't think this should mention substitution. With that tweak the C++
changes are OK.
Since r268321 we can call digest_init even in a template, when the compound
literal isn't instantiation-dependent. Consequently, when we get to
case RANGE_FOR_STMT in tsubst_expr, RANGE_FOR_EXPR might already have been
digested, as in this case, where before digesting it was
{*((struct S *)
On 2/7/19 1:57 PM, Martin Sebor wrote:
+ /* The original numeric size as seen in the source code after
+ any substitution and before conversion to size_t. */
I don't think this should mention substitution. With that tweak the C++
changes are OK.
Jason
On 2/5/19 4:39 AM, Paolo Carlini wrote:
Hi,
On 04/02/19 17:48, Jason Merrill wrote:
On Mon, Feb 4, 2019 at 11:00 AM Paolo Carlini
wrote:
On 04/02/19 15:47, Jason Merrill wrote:
On 2/1/19 3:52 PM, Paolo Carlini wrote:
Hi,
I think that this ICE on invalid (and valid, for c++17+) can be in
Hi!
I've noticed pre_and_rev_post_order_compute_fn is one of (apparently many)
functions that take a struct function * argument and accept any function, as
long as it is cfun. For a patch I've been working on I actually need it
to handle other functions as well and in this case it is trivial to
Hi!
As mentioned in the PR, given that during expansion we expand ARRAY_REFs
using get_inner_reference that casts ARRAY_*REF indexes to sizetype, all the
bits above sizetype are ignored (whether one uses long long indexes on
32-bit targets or __int128 indexes on 64-bit ones), so I think it is
Hi!
The following testcase ICEs on ppc64le. The problem is that
copy_reg_eh_region_note_* functions accept either some instruction, or
REG_EH_REGION note directly. To differentiate between those it uses INSN_P
test (and returns early if the insn doesn't contain any REG_EH_REGION
notes). If the
OImode and TImode moves must be done in XImode to access upper 16
vector registers without AVX512VL. With AVX512VL, we can access
upper 16 vector registers in OImode and TImode.
PR target/89229
* config/i386/i386.md (*movoi_internal_avx): Set mode to XI for
upper 16
On February 7, 2019 9:10:15 PM GMT+01:00, David Malcolm
wrote:
>PR tree-optimization/89235 reports an ICE inside
>-fsave-optimization-record
>whilst reporting the inlining chain of of the location_t in the
>vect_location global.
>
>This is very similar to PR tree-optimization/86637, fixed in
On Thu, Feb 07, 2019 at 03:04:21PM -0500, Michael Ploujnikov wrote:
> 2019-02-07 Michael Ploujnikov
>
> PR middle-end/89150
> * bitmap.c (test_bitmap_tree_marking): New test.
> (NOT_NULL_OR_GARBAGE): For shortening
> test_bitmap_tree_marking.
> (bitmap_c_tests):
On 2019-02-04 11:39 a.m., Richard Biener wrote:
> On February 4, 2019 5:07:00 PM GMT+01:00, Jeff Law wrote:
>> On 2/4/19 6:15 AM, Richard Biener wrote:
>>>
>>> When I introduced tree-form bitmaps I forgot to think about GC.
>>> The following drops the chain_prev annotation to make the marker
>>>
PR tree-optimization/89235 reports an ICE inside -fsave-optimization-record
whilst reporting the inlining chain of of the location_t in the
vect_location global.
This is very similar to PR tree-optimization/86637, fixed in r266821.
The issue is that the inlining chains are read from the
On 2/7/19 9:10 AM, Jason Merrill wrote:
On 2/5/19 4:55 PM, Martin Sebor wrote:
On 2/5/19 12:14 PM, Jason Merrill wrote:
On 2/5/19 1:46 PM, Martin Sebor wrote:
On 2/1/19 7:41 AM, Jason Merrill wrote:
On 1/31/19 5:49 PM, Martin Sebor wrote:
On 1/30/19 3:15 PM, Jason Merrill wrote:
On 1/29/19
New test committed as obvious at revision r268656.
Dominique
Hi Steve,
>> After special cases you could do something like t = mask2 + (HWI_1U <<
>> shift);
>> return t == (t & -t) to check for a valid bfi.
>
> I am not sure I follow this logic and my attempts to use this did not
> work so I kept my original code.
It's similar to the initial code in
Standard scalar operation patterns which preserve the rest of the vector
look like
(vec_merge:V2DF
(vec_duplicate:V2DF
(op:DF (vec_select:DF (reg/v:V2DF 85 [ x ])
(parallel [ (const_int 0 [0])]))
(reg:DF 87))
(reg/v:V2DF 85 [ x ])
My previous patch failed to only run an arm test on arm architecture.
This adds that condition to the test.
Committed to trunk as obvious.
gcc/testsuite/ChangeLog:
2019-02-07 Matthew Malcomson
* gcc.dg/rtl/arm/ldrd-peepholes.c: Only run on arm
### Attachment also
I'd like to ping for this patch:
https://gcc.gnu.org/ml/gcc-patches/2019-01/msg01779.html
Thanks
Bernd.
On 1/31/19 12:38 PM, Bernd Edlinger wrote:
> Hi,
>
> I have an issue with the installation of gcc when configured with
> --enable-languages=all
> on an arm-target where install-sh is used,
On Thu, Feb 7, 2019 at 5:44 AM H.J. Lu wrote:
>
> PR target/89229
> * config/i386/i386.md (*movoi_internal_avx): Set mode to OI
> for TARGET_AVX512VL.
> (*movti_internal): Set mode to TI for TARGET_AVX512VL.
OK.
Thanks,
Uros.
> ---
> gcc/config/i386/i386.md | 4
On 2/7/19 2:24 AM, Alexandre Oliva wrote:
From: Alexandre Oliva
A lambda capture variable initialized with a lambda expr taking more
than one parameter got us confused.
The first problem was that the parameter list was cut short during
tsubsting because we tsubsted it with
Hi Honza,
> PR ipa/88711
> * gfortran.dg/pr79966.f90: Xfail for time being.
> Index: ../../gcc/testsuite/gfortran.dg/pr79966.f90
> ===
> --- ../../gcc/testsuite/gfortran.dg/pr79966.f90 (revision 268579)
> +++
Hi,
I have added the testcase for PR79966 to test that tp_sum is inlined
becuase it matters for performance of that benchmark. Sadly it is not
inlined anymore because it was inlined due to accounting bug I fixed in
January.
I do not see how to make inliner to do the inlining here except for
On 2/5/19 8:58 PM, Alexandre Oliva wrote:
On Feb 5, 2019, Jason Merrill wrote:
On Tue, Feb 5, 2019 at 1:37 AM Alexandre Oliva wrote:
On Jan 31, 2019, Jason Merrill wrote:
Let's use strip_using_decl instead
Aah, nice! Thanks, I'll make the changes, test them, and post a new patch.
The tasking is terminally broken on SPARC/Linux with the mainline compiler.
The problem is also visible on other branches if you compile the runtime with
assertions enabled.
Tested on SPARC64/Linux, applied on all active branches.
2019-02-07 Eric Botcazou
*
On 2/5/19 4:55 PM, Martin Sebor wrote:
On 2/5/19 12:14 PM, Jason Merrill wrote:
On 2/5/19 1:46 PM, Martin Sebor wrote:
On 2/1/19 7:41 AM, Jason Merrill wrote:
On 1/31/19 5:49 PM, Martin Sebor wrote:
On 1/30/19 3:15 PM, Jason Merrill wrote:
On 1/29/19 7:15 PM, Martin Sebor wrote:
+ /*
This patch fixes several problems with the vec_xl/vec_xst builtins:
- vec_xl/vec_xst needs to use the alignment of the scalar memory
operand for the vector type reference. This is required to emit the
proper vl/vst alignment hints.
- vec_xl / vec_xld2 / vec_xlw4 should accept const pointer
On 2/7/19 2:46 AM, Segher Boessenkool wrote:
Hi Martin,
On Wed, Feb 06, 2019 at 05:28:08PM -0700, Martin Sebor wrote:
void
-__clear_cache (char *beg __attribute__((__unused__)),
- char *end __attribute__((__unused__)))
+__clear_cache (void *beg __attribute__((__unused__)),
+
Hi!
Another month have passed since my last 8.x backporting effort,
thus I've backported following 32 patches from trunk to 8.x,
bootstrapped/regtested on x86_64-linux and i686-linux and committed.
Jakub
2019-02-07 Jakub Jelinek
Backported from mainline
2019-01-07
>>
>
> Please add the PR marker to the testsuite ChangeLog as well.
> I've been following this PR a bit from the sidelines, I believe a
> substantial amount of code
> (and one of the testcases) was written by Jakub, so please add him to
> the ChangeLog entries as well.
>
> This looks ok to
On 31/01/19 21:08 -0800, Thomas Rodgers wrote:
Update C++17 parallel algorithms to LLVM/MIT licensed upstream sources
Some lines in bits/c++config.h need to be split before 80 columns
(with a backslash if the split is in the middle of a preprocessor
condition obviously).
There are loads of
Hi!
On Wed, Feb 06, 2019 at 11:08:44PM +0100, Eric Botcazou wrote:
> as reported e.g. at https://gcc.gnu.org/ml/gcc-help/2018-11/msg00038.html,
> the
> 7 series of compilers started to use FP instructions for simple 64-bit
> integer
> loads/stores in unexpected ways. Consider:
> The
Hi All,
This fixes a missing = that would cause the array initializer to be a C++
initializer instead of a C one, causing a warning when building with pre-C++11
standards compiler.
Committed under the GCC obvious rules.
gcc/ChangeLog:
2019-02-07 Tamar Christina
*
Hi All,
Since this hasn't been reviewed yet anyway I've updated this patch to also fix
the memory leaks etc.
--
This patch makes the feature detection code for AArch64 GCC not add features
automatically when the feature had no hwcaps string to match against.
This means that -mcpu=native no
Hi Gerard,
>
> On Wed, 6 Feb 2019, Tamar Christina wrote:
> > I've updated the patch with your suggested changes and have grouped
> > the Arm and AArch64 targets a bit.
>
> Thanks, Tamar!
>
> > Ok for commit?
>
> Yes, I had meant to imply this in my original review. :-)
>
> Only note is that
On Wed, 6 Feb 2019, Tamar Christina wrote:
> I've updated the patch with your suggested changes and have grouped
> the Arm and AArch64 targets a bit.
Thanks, Tamar!
> Ok for commit?
Yes, I had meant to imply this in my original review. :-)
Only note is that this seems to hop from to ,
Bootstrapped and regtested on s390x-redhat-linux.
Implementation of section anchors in S/390 back-end added in r266741
broke jump labels in S/390 Linux kernel [1]. Currently jump labels
pass global variable addresses to .quad directive in inline assembly
using "X" constraint. In the past this
On 23/12/18 21:27 -0500, Tom Honermann wrote:
Attached is a revised patch that addresses changes in P0482R6.
Changes from the prior patch include:
- Updated the value of the __cpp_char8_t feature test macro to 201811.
Tested on x86_64-linux.
There are quite a few additional changes needed
Hi James,
On 06/02/19 17:33, James Greenhalgh wrote:
On Mon, Feb 04, 2019 at 04:23:32AM -0600, Kyrill Tkachov wrote:
Hi all,
Richard raised a concern about the RTL we use to represent the AdvSIMD SABD
(vector signed absolute difference) instruction.
We currently represent it as ABS (MINUS op1
Hi Martin,
On Wed, Feb 06, 2019 at 05:28:08PM -0700, Martin Sebor wrote:
> void
> -__clear_cache (char *beg __attribute__((__unused__)),
> -char *end __attribute__((__unused__)))
> +__clear_cache (void *beg __attribute__((__unused__)),
> +void *end
On 23/12/18 21:27 -0500, Tom Honermann wrote:
Attached is a revised patch that addresses changes in P0482R6.
Changes from the prior patch include:
- Updated the value of the __cpp_char8_t feature test macro to 201811.
Tested on x86_64-linux.
Thanks, Tom, this is great work!
The front-end
Hi all,
For the Dot Product instructions we have the scheduling types neon_dot and
neon_dot_q for the 128-bit versions.
It seems that we're only using the former though, not assigning the neon_dot_q
type anywhere.
This patch fixes that by adding the mode attribute suffix to the type,
Hi,
this patch implements vector copysign using vector select on S/390.
Regtested and bootstrapped on s390x.
Regards
Robin
--
gcc/ChangeLog:
2019-02-07 Robin Dapp
* config/s390/vector.md: Implement vector copysign.
gcc/testsuite/ChangeLog:
2019-02-07 Robin Dapp
*
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