Re: libgo patch committed: Add S/390 support to internal/cpu package

On Fri, Feb 15, 2019 at 08:59:29PM +0100, Matthias Klose wrote: > On 15.02.19 15:52, Ian Lance Taylor wrote: > > This patch by Robin Dapp adds S/390 support to the internal/cpu > > package. This partially addresses PR 89123. I bootstrapped it on > > x86_64-pc-linux-gnu, which means little.

[PATCH] Decrease {i386,sse}.md global state by 12KB

Hi! This is something I've noticed in a s390 change I'll post soon (where it was even completely unnecessary), but it applies to i386 backend too. Seems we have lots of .bss global state, 66x 64-byte and 61x 128-byte long static buffers. Instead of doing static char buf[128]; ...

[PATCH] Improve mem = STRING_CST expansion (PR rtl-optimization/66152)

Hi! On the following testcase, we've regressed in bar since 8.x, in 8.x store merging came up with mem = 64-bit constant, but starting with the change to transform {0,1,2,3,4,5,6,7} char initializers into STRING_CSTs, we don't do that anymore. The mem = STRING_CST expansion can do that, but only

[PATCH] Teach evrp that main's argc argument is always non-negative for C family (PR tree-optimization/89350)

Hi! Both the C and C++ standard guarantee that the argc argument to main is non-negative, the following patch sets (or adjusts) the corresponding SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also propagate etc. I had to change one testcase because it started optimizing it

Re: C++ PATCH for c++/89217 - ICE with list-initialization in range-based for loop

On 2/11/19 6:03 PM, Marek Polacek wrote: On Mon, Feb 11, 2019 at 01:43:36PM -0500, Jason Merrill wrote: On 2/7/19 6:02 PM, Marek Polacek wrote: Since r268321 we can call digest_init even in a template, when the compound literal isn't instantiation-dependent. Right. And since digest_init

Re: [PATCH] v2: Fix excess warnings from -Wtype-limits with location wrappers (PR c++/88680)

On 2/14/19 4:20 PM, David Malcolm wrote: On Thu, 2019-02-14 at 17:32 +0100, Jakub Jelinek wrote: On Thu, Feb 14, 2019 at 11:26:15AM -0500, David Malcolm wrote: There's an asymmetry in the warning; it's looking for a comparison of a LHS expression against an RHS constant 0, spelled as "0". If

Re: [C++ PATCH] preview: Fix braces around scalar initializer (C++/88572) Inbox x

On 2/14/19 7:09 PM, will wray wrote: Thanks Jason. Adding this 'else if' condition afterwards seems to work: else if (BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT (stripped_init,0)->value)) { if (complain & tf_error) error ("too many braces around scalar

Re: [PATCH] document __builtin_is_constant_evaluated

On 2/13/19 4:33 PM, Martin Sebor wrote: Index: gcc/doc/extend.texi === --- gcc/doc/extend.texi (revision 268856) +++ gcc/doc/extend.texi (working copy) @@ -12890,6 +12890,22 @@ built-in in this case, because it has no opportuni

Re: [PATCH] document __has_attribute and __has_include

On 2/13/19 2:46 PM, Martin Sebor wrote: The attached patch adds documentation for the __has_attribute (and __has_cpp_attribute) and __has_include operators added in r215752. Thanks! I was a little unsure where to add this, whether the preprocessor manual or the GCC manual, or both.  It seems

Re: [PATCH doc] correct/expand -Wreturn-type

On 2/6/19 11:15 AM, Martin Sebor wrote: [snip] But whatever.  Attached is a change with the subsentences reversed. This version of the patch is OK. -Sandra

Re: [PATCH doc] correct/improve -Wmissing-attributes and -Wattribute-alias

On 2/6/19 9:16 AM, Martin Sebor wrote: The manual documents the -Wno-missing-attributes form of the option as if it was enabled by default, even though it's enabled by -Wall (I can't get this -Wno- convention straight in my head).  I also got private comments on the documentation of the option

[PATCH 32/42] i386: Emulate MMX pshufb with SSE version

Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE.

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote: > > On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > > > On x86-64, since __m64 is returned and passed in XMM registers, we can > > emulate MMX intrinsics with SSE instructions. To support it, we added > > > > #define TARGET_MMX_WITH_SSE

[PATCH 40/42] i386: Allow MMX intrinsic emulation with SSE

Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA by default with TARGET_MMX_WITH_SSE. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit mode since MMX intrinsics can be emulated wit SSE. gcc/ PR target/89021 *

[PATCH 26/42] i386: Emulate MMX umulv1siv1di3 with SSE2

Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation support. (*sse2_umulv1siv1di3): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 26

[PATCH 22/42] i386: Emulate MMX mmx_uavgv8qi3 with SSE

Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 25

[PATCH 28/42] i386: Emulate MMX ssse3_phwv4hi3 with SSE

Emulate MMX ssse3_phwv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phwv4hi3): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 27/42] i386: Make _mm_empty () as NOP when MMX is disabled

With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP when MMX is disabled. PR target/89021 * config/i386/mmx.md (mmx_): Renamed to ... (mmx__1): This. (mmx_): New expander. --- gcc/config/i386/mmx.md | 29 - 1 file

[PATCH 12/42] i386: Emulate MMX vec_dupv2si with SSE

Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow broadcast from integer register for AVX512BW with TARGET_AVX512VL. Only SSE register source operand is allowed. PR target/89021 * config/i386/constraints.md (Yw): New constraint. * config/i386/mmx.md

[PATCH 37/42] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE

From: Uros Bizjak 2019-02-14 Uroš Bizjak PR target/89021 * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute. * config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto. (*vec_concatv2sf_sse): Ditto. (*vec_concatv2si_sse4_1): Ditto.

[PATCH 39/42] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set mmx_ok to true if TARGET_MMX_WITH_SSE is true. (ix86_expand_vector_init_one_nonzero): Likewise. (ix86_expand_vector_init_one_var): Likewise.

[PATCH 41/42] i386: Enable TM MMX intrinsics with SSE2

This pach enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with SSE2. --- gcc/config/i386/i386.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

[PATCH 21/42] i386: Emulate MMX maskmovq with SSE2 maskmovdqu

Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by zero-extending source and mask operands to 128 bits. Handle unmapped bits 64:127 at memory address by adjusting source and mask operands together with memory address. PR target/89021 * config/i386/xmmintrin.h:

[PATCH 25/42] i386: Emulate MMX movntq with SSE2 movntidi

Emulate MMX movntq with SSE2 movntidi. Only register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git

[PATCH 35/42] i386: Emulate MMX abs2 with SSE

Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/sse.md

[PATCH 24/42] i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH 31/42] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff

[PATCH 38/42] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH 36/42] i386: Correct _pmulhrsw3[_mask]

There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require AVX2. To support TARGET_MMX_WITH_SSE, replace nonimmediate_operand with register_pmulhrswmem_operand in _pmulhrsw3. PR target/89372 * config/i386/predicates.md (register_pmulhrswmem_operand): New.

[PATCH 30/42] i386: Emulate MMX ssse3_pmaddubsw with SSE

Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 29/42] i386: Emulate MMX ssse3_phdv2si3 with SSE

Emulate MMX ssse3_phdv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phdv2si3): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 33/42] i386: Emulate MMX ssse3_psign3 with SSE

Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_psign3): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 34/42] i386: Emulate MMX ssse3_palignrdi with SSE

Emulate MMX version of palignrq with SSE version by concatenating 2 64-bit MMX operands into a single 128-bit SSE operand, followed by SSE psrldq. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_palignrdi): Changed to

[PATCH 19/42] i386: Emulate MMX mmx_pmovmskb with SSE

Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 15/42] i386: Emulate MMX sse_cvtpi2ps with SSE

Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add

[PATCH 17/42] i386: Emulate MMX mmx_pinsrw with SSE

Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 33

[PATCH 20/42] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE

Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. ---

[PATCH 13/42] i386: Emulate MMX pshufw with SSE

Emulate MMX pshufw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_pshufw_1): Add SSE emulation. (*vec_dupv4hi): Changed to define_insn_and_split

[PATCH 14/42] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE

Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE. PR target/89021 * config/i386/sse.md (sse_cvtps2pi): Add SSE emulation. (sse_cvttps2pi): Likewise. --- gcc/config/i386/sse.md | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff

[PATCH 23/42] i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 26

[PATCH 05/42] i386: Emulate MMX mulv4hi3 with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. (mulv4hi3): New. (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 06/42] i386: Emulate MMX smulv4hi3_highpart with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 18/42] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE

Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_v8qi3): Likewise. (smaxmin:v4hi3): New.

[PATCH 16/42] i386: Emulate MMX mmx_pextrw with SSE

Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 11/42] i386: Emulate MMX mmx_eq/mmx_gt3 with SSE

Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_eq3): Also allow TARGET_MMX_WITH_SSE. (*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. (mmx_gt3): Likewise. ---

[PATCH 10/42] i386: Emulate MMX mmx_andnot3 with SSE

Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_andnot3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 18 +++--- 1 file changed, 11 insertions(+), 7

[PATCH 07/42] i386: Emulate MMX mmx_pmaddwd with SSE

Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25

[PATCH 09/42] i386: Emulate MMX 3 with SSE

Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:mmx_3): Also allow TARGET_MMX_WITH_SSE. (any_logic:3): New. (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE. Add SSE support.

[PATCH 08/42] i386: Emulate MMX ashr3/3 with SSE

Emulate MMX ashr3/3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_ashr3): Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. (mmx_3): Likewise. (ashr3): New. (3): Likewise. ---

[PATCH 02/42] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2

Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. 2019-02-08 H.J. Lu Uros Bizjak PR target/89021 * config/i386/i386-protos.h

[PATCH 04/42] i386: Emulate MMX plusminus/sat_plusminus with SSE

Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI. (plusminus:mmx_3): Check TARGET_MMX_WITH_SSE. (sat_plusminus:mmx_3): Likewise.

[PATCH 01/42] i386: Allow MMX register modes in SSE registers

In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386-c.c (ix86_target_macros_internal): Define __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. * config/i386/i386.c

[PATCH 00/42] V7: Emulate MMX intrinsics with SSE

On x86-64, since __m64 is returned and passed in XMM registers, we can emulate MMX intrinsics with SSE instructions. To support it, we added #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) ;; Define instruction set of MMX instructions (define_attr "mmx_isa"

[PATCH 03/42] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX

Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX, move bits 64:127 to bits 0:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/i386-protos.h (ix86_split_mmx_punpck): New prototype. *

Re: Fortran vector math header

On Tue, Feb 05, 2019 at 01:47:57PM +0100, Martin Liška wrote: > > gcc/fortran/ChangeLog: > > 2019-01-24 Martin Liska > > * decl.c (gfc_match_gcc_builtin): Add support for filtering > of builtin directive based on multilib ABI name. > > gcc/testsuite/ChangeLog: > > 2019-01-24

Go patch committed: Use __builtin_dwarf_cfa for getcallersp

This patch by Cherry Zhang changes the Go compiler and runtime to use __builtin_dwarf_cfa for getcallersp. Currently, the compiler lowers runtime.getcallersp to __builtin_frame_address(1). In the C side of the runtime, getcallersp is defined as __builtin_frame_address(0). They don't match.

[testsuite] Couple of g++.dg/asan tweaks

One of the tests in g++.dg/asan/asan_oob_test.cc uses unaligned memory accesses and g++.dg/asan/function-argument-3.C assumes a specific kind of calling conventions for vectors. Tested on SPARC64/Linux, applied on the mainline. 2019-02-15 Eric Botcazou *

[SPARC] Small ASAN fixes

This automatically passes -funwind-tables when ASAN is used on Linux, as done for other architectures, and also adjusts the shadow offset in 64-bit mode. Tested on SPARC64/Linux, applied on the mainline. 2019-02-15 Eric Botcazou * config/sparc/linux.h (ASAN_CC1_SPEC): Define.

Re: [PATCH] Avoid assuming valid_constant_size_p argument is a constant expression (PR 89294)

On 2/15/19 3:46 PM, Eric Botcazou wrote: I'm ready to commit the patch once it's approved, and have been since the day the problem was reported. Maybe CCing whoever approved the previous patch would help? I just pinged the patch a few minutes ago and CC'd Jason. Sorry about any trouble this

Re: [PATCH] Avoid assuming valid_constant_size_p argument is a constant expression (PR 89294)

> I'm ready to commit the patch once it's approved, and have been since > the day the problem was reported. Maybe CCing whoever approved the previous patch would help? -- Eric Botcazou

Re: [PATCH] Avoid assuming valid_constant_size_p argument is a constant expression (PR 89294)

Ping: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00857.html Jason, since you approved the original patch, can you please also review this one? Due to the Ada test breakage there seems to be some anxiety about getting the problem corrected soon. Thanks Martin On 2/11/19 6:13 PM, Martin

[PATCH, og8] Don't rescan "attach" node for dereferenced struct member

Hi, The following (og8 branch) patch added support for attaching/detaching from dereferenced struct members: https://gcc.gnu.org/ml/gcc-patches/2019-01/msg01778.html Unfortunately I made a mistake in the portion of that patch that inserts new alloc and firstprivate_pointer nodes for the struct

Re: [patch] Disable store merging in asan_expand_mark_ifn

> > OK, revised patch attached. I have manually verified that it yields the > > expected result for an array of long doubles on 64-bit SPARC. > > > > > > 2019-02-12 Eric Botcazou > > > > * asan.c (asan_expand_mark_ifn): Take into account the alignment of > > the object to pick the

Re: [PATCH] Avoid assuming valid_constant_size_p argument is a constant expression (PR 89294)

On 2/15/19 12:24 AM, Eric Botcazou wrote: The attached patch removes the assumption introduced earlier today in my fix for bug 87996 that the valid_constant_size_p argument is a constant expression. I couldn't come up with a C/C++ test case where this isn't true but apparently it can happen in

Go patch committed: Don't use a nil check for the write barrier

This patch to the Go frontend by Than McIntosh tweaks the recipe for generating writeBarrier loads to insure that the dereference expr is marked as not requiring a nil check. This should fix gcc PR 89368. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian

[PR fortran/89077, patch, part 3] - ICE using * as len specifier for character parameter

The attached patch is the third in a series for the above PR. This one fixes erroneous padding with garbage characters in some declaration and initialization expressions. The issue here was that expr->representation is set when either Hollerith strings are used or a TRANSFER statement is

[PATCH] i386: Fix ')' in VALID_MMX_REG_MODE

Replace "(MODE == V1DImode)" with "(MODE) == V1DImode". * config/i386/i386.h (VALID_MMX_REG_MODE): Correct the misplaced ')'. --- gcc/ChangeLog | 5 + gcc/config/i386/i386.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog

Re: libgo patch committed: Add S/390 support to internal/cpu package

On 15.02.19 15:52, Ian Lance Taylor wrote: > This patch by Robin Dapp adds S/390 support to the internal/cpu > package. This partially addresses PR 89123. I bootstrapped it on > x86_64-pc-linux-gnu, which means little. Committed to mainline. fails in the -m31 multilib variant with libtool:

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 7:20 PM H.J. Lu wrote: > > I went through the code again, and looks OK in general, modulo > > mmx_nonimmediate_operand issue and a couple of minor issues. > > > > Please substitute nonimmediate_operand predicate with > > mmx_nonimmediate_operand in expanders and insn

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote: > > On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > > > On x86-64, since __m64 is returned and passed in XMM registers, we can > > emulate MMX intrinsics with SSE instructions. To support it, we added > > > > #define TARGET_MMX_WITH_SSE

[PATCH, i386]: Add missing TARGET_FPMATH_DEFAULT_P to darwin.h

Darwin defines its own TARGET_FPMATH_DEFAULT, which should be accompanied by corresponding TARGET_FPMATH_DEFAULT_P. Patch adds missing define. While looking around, I also fixed various whitespace issues in the header. BTW: The header file still defines TARGET_64BIT which is horribly out of

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > On x86-64, since __m64 is returned and passed in XMM registers, we can > emulate MMX intrinsics with SSE instructions. To support it, we added > > #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) > > ;; Define instruction set of MMX

Re: [PATCH 28/42] i386: Make _mm_empty () as NOP when MMX is disabled

On Fri, Feb 15, 2019 at 3:03 PM H.J. Lu wrote: > > With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP > when MMX is disabled. > > PR target/89021 > * config/i386/mmx.md (EMMS): Also allow TARGET_MMX_WITH_SSE. > (mmx_): Generate "" only when MMX is

[Committed][PATCH][GCC][Arm] Remove alternative from neon_softfp_fp16 directive.

Hi All, There's a bit of a disconnect between the feature flags that don't test the fpu and ones that do when the test itself also forces an architecture. The forcing of the architecture would change the defaults and without explicitly giving the correct fpu again the test would fail. I don't

Re: [PATCH][DOC] Document new features for GCC 9.

On 2/14/19, David Malcolm wrote: > On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote: >> On 2/13/19 6:48 AM, Martin Liška wrote: >> > Hi. >> > >> > I'm sending patch where I document changes I made during GCC 9 >> > development. I would appreciate both language and factical comments >> >

Re: [PATCH][GCC][DOC] Remove obsolete arm and aarch64 CPU names from invoke.texi

On 19/01/2019 23:37, Gerald Pfeifer wrote: > On Thu, 10 Jan 2019, Sam Tebbs wrote: >>> I believe this should also be covered in the GCC 9 release notes >>> at https://gcc.gnu.org/gcc-9/changes.html ? >> Sorry for the late reply. My email filters seem to have stumbled a bit >> so I didn't pick

Re: [PATCH 02/42] i386: Add mmx_nonimmediate_operand

On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > True if the operand is a register or an nonimmediate operand when > TARGET_MMX_WITH_SSE is false. > > PR target/89021 > * config/i386/predicates.md (mmx_nonimmediate_operand): New. > --- > gcc/config/i386/predicates.md | 7

GCC 8.3 Status Report (2019-02-15)

Status == The GCC 8 branch is now frozen for blocking regressions and documentation fixes only, all changes to the branch require a RM approval now. Quality Data Priority # Change from last report --- --- P10 P2

Re: [PATCH 17/42] i386: Emulate MMX mmx_pextrw with SSE

On Fri, Feb 15, 2019 at 6:03 AM H.J. Lu wrote: > > Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is > allowed. > > PR target/89021 > * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. > --- > gcc/config/i386/mmx.md | 16 +--- > 1 file changed,

Bugs in extended C interop

Dear Paul, I've started putting together my observations on the current status of the F2018 C interop extensions in gfortran 9.0. See the PRs 89363, 89364, 89365, 89366: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89363 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89364

libgo patch committed: Add S/390 support to internal/cpu package

This patch by Robin Dapp adds S/390 support to the internal/cpu package. This partially addresses PR 89123. I bootstrapped it on x86_64-pc-linux-gnu, which means little. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

Re: Go patch committed: Harmonize types referenced by both C and Go

On Fri, Feb 15, 2019 at 4:03 AM Rainer Orth wrote: > > Andreas Schwab writes: > > > This breaks non-split-stack builds. > > > > ../../../libgo/runtime/stack.c: In function 'doscanstack1': > > ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of > > 'scanstackblock' makes integer

[PR 89330] Avoid adding dead speculative edges to inlinig heap

Hi, Martin discovered that inliner was adding deleted call graph edges to its heap when supposedly processing newly discovered direct edges. The problem is that a new edge created in the speculation part of the indirect inlining machinery created speculative edges that were immediately

[PATCH 29/42] i386: Emulate MMX ssse3_phwv4hi3 with SSE

Emulate MMX ssse3_phwv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phwv4hi3): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 30/42] i386: Emulate MMX ssse3_phdv2si3 with SSE

Emulate MMX ssse3_phdv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phdv2si3): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 10/42] i386: Emulate MMX 3 with SSE

Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:3): New. (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 27 --- 1 file

[PATCH 20/42] i386: Emulate MMX mmx_pmovmskb with SSE

Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 38/42] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH 33/42] i386: Emulate MMX pshufb with SSE version

Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE.

[PATCH 28/42] i386: Make _mm_empty () as NOP when MMX is disabled

With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP when MMX is disabled. PR target/89021 * config/i386/mmx.md (EMMS): Also allow TARGET_MMX_WITH_SSE. (mmx_): Generate "" only when MMX is enabled. --- gcc/config/i386/mmx.md | 6 -- 1 file changed,

[PATCH 24/42] i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 22

[PATCH 40/42] i386: Allow MMX intrinsic emulation with SSE

Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA by default with TARGET_MMX_WITH_SSE. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit mode since MMX intrinsics can be emulated wit SSE. gcc/ PR target/89021 *

[PATCH 25/42] i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH 27/42] i386: Emulate MMX umulv1siv1di3 with SSE2

Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation support. (*sse2_umulv1siv1di3): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 22

[PATCH 23/42] i386: Emulate MMX mmx_uavgv8qi3 with SSE

Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 21

[PATCH 41/42] i386: Enable TM MMX intrinsics with SSE2

This pach enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with SSE2. --- gcc/config/i386/i386.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

[PATCH 36/42] i386: Emulate MMX abs2 with SSE

Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/sse.md

[PATCH 32/42] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff

[PATCH 21/42] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE

Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. ---

[PATCH 17/42] i386: Emulate MMX mmx_pextrw with SSE

Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git

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