Re: [PATCH v2] vect/rs6000: Support vector with length cost modeling

On Wed, Jul 22, 2020 at 3:26 AM Kewen.Lin wrote: > > Hi Richard, > > on 2020/7/21 下午3:57, Richard Biener wrote: > > On Tue, Jul 21, 2020 at 7:52 AM Kewen.Lin wrote: > >> > >> Hi, > >> > >> This patch is to add the cost modeling for vector with length, > >> it mainly follows what we generate for v

Re: [PATCH] c++: decl_constant_value and unsharing [PR96197]

On Tue, Jul 21, 2020 at 9:08 PM Patrick Palka via Gcc-patches wrote: > > In the testcase from the PR we are seeing excessive memory use (> 5GB) > during constexpr evaluation, almost all of which is due to the call to > decl_constant_value in the VAR_DECL/CONST_DECL branch of > cxx_eval_constant_ex

Re: [PATCH] libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCS

On Tue, Jul 21, 2020 at 8:24 PM Maciej W. Rozycki wrote: > > Complement commit b932f770f70d ("x86_64 frame unwind info"), SVN r46374, > , and replace > `-fexceptions -fnon-call-exceptions' with `-fasynchronous-unwind-tables' > in LIB2_DIVMO

[PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.

Those two define_insns have same pattern, and _load_mask would always be matched since it show up earlier in the md file, and it may lose some opportunity in pass_reload since _load_mask only have constraint "0C" for operand2, and "v" constraint in _vblendm would never be matched. 2020-07-21 Ho

[PATCH] doc: fix a typo in languages.texi

hi, This patch fix a typo in languages.texi. Regards! weiwt --- gcc/doc/languages.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/doc/languages.texi b/gcc/doc/languages.texi index 70641482a1d..c6144f253c5 100644 --- a/gcc/doc/languages.texi +++ b/gcc/doc/languages.te

[PATCH PR96053] Add "#pragma GCC no_reduc_chain"

Hi, It is the patch to add "#pragma GCC no_reduc_chain" for pr96053. It only completes the front end of C language. For the testcase, it successfully skipped doing slp by finding sequences from reduction chains. Without "#pragma GCC no_reduc_chain", it will fail to do vectorization. Please

gcc.dg/no_profile_instrument_function-attr-1.c: Adjust for NO_DOT_IN_LABEL

mmix-knuth-mmixware is a NO_DOT_IN_LABEL target, so it gets a "_" instead of the "." in the identifier of interest. Also tested and compared to the output for cris-elf which is "regular" regarding labels: there are no "false positive" identifiers there. The "." in a TCL bracket expression matches

[PATCH] rs6000: Rename adjust_vectorization_cost

Hi, This trivial patch is to rename adjust_vectorization_cost to adjust_vect_cost_per_stmt. Hope it's more meaningful, as well as to avoid the confusion between the possible to be landed function "adjust_vect_cost" and "adjust_vectorization_cost". Even without "adjust_vect_cost", I guess it's s

[PATCH v2] vect/rs6000: Support vector with length cost modeling

Hi Richard, on 2020/7/21 下午3:57, Richard Biener wrote: > On Tue, Jul 21, 2020 at 7:52 AM Kewen.Lin wrote: >> >> Hi, >> >> This patch is to add the cost modeling for vector with length, >> it mainly follows what we generate for vector with length in >> functions vect_set_loop_controls_directly and

Re: [PATCH] dse: Remove partial load after full store for high part access[PR71309]

On Tue, Jul 21, 2020 at 06:37:29PM -0400, David Edelsohn wrote: > On Tue, Jul 21, 2020 at 5:54 PM Segher Boessenkool > wrote: > > always (the target cannot run the resulting code, but we have many other > > options like that, starting with -mcpu=). David, what is your > > preference? > > > > The

Re: [PATCH] Add TARGET_LOWER_LOCAL_DECL_ALIGNMENT [PR95237]

On Tue, Jul 21, 2020 at 12:50 AM Richard Biener wrote: > > On Tue, Jul 21, 2020 at 7:16 AM Sunil Pandey wrote: > > > > On Mon, Jul 20, 2020 at 5:06 AM Richard Biener > > wrote: > > > > > > On Sat, Jul 18, 2020 at 7:57 AM Sunil Pandey wrote: > > > > > > > > On Fri, Jul 17, 2020 at 1:22 AM Richar

Re: PATCH 6/6 ver 5] rs6000 Add vector blend, permute builtin support

Hi! On Tue, Jul 21, 2020 at 10:28:01AM -0700, Carl Love wrote: > [PATCH 6/6] rs6000 Add vector blend, permute builtin support > > * config/rs6000/altivec.h (vec_blendv, vec_permx): Add define. > * config/rs6000/altivec.md (UNSPEC_XXBLEND, UNSPEC_XXPERMX.): New > unspecs. (stra

Re: [PATCH] dse: Remove partial load after full store for high part access[PR71309]

On Tue, Jul 21, 2020 at 5:54 PM Segher Boessenkool wrote: > > Hi! > > On Tue, Jul 21, 2020 at 05:54:27AM -0500, Xiong Hu Luo wrote: > > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > > @@ -3,7 +3,7 @@ > >

Re: [PATCH 5/6 ver 5] rs6000, Add vector splat builtin support

Hi Carl, On Tue, Jul 21, 2020 at 10:32:53AM -0700, Carl Love wrote: >Looked at comment about changing the return type of > rs6000_const_f32_to_i32 (rtx operand) > from long to int or unsigned int. If I make that change I get an ICE > on insn not recognized. Let's leave that for

[Patch fortran] PR 93567 - G edit descriptor uses E instead of F editing in rounding mode UP

I am not set up to commit on git, someone will have to do it for me. TIA Dominique --- ../_clean/libgfortran/io/write_float.def 2020-06-13 03:11:55.0 +0200 +++ libgfortran/io/write_float.def 2020-07-21 23:03:08.0 +0200 @@ -987,16 +987,19 @@ determine_en_precision (st_parameter_dt

[Patch, fortran] PR 93592 - Invalid UP/DOWN rounding with EN descriptor

The fix is obvious (I have added a comment). The tests are probably an overkill, but it does not hurt. I am not set up to commit on git, someone will have to do it for me. TIA Dominique --- ../_clean/libgfortran/io/write_float.def 2020-06-13 03:11:55.0 +0200 +++ libgfortran/io/write_fl

Re: [PATCH] dse: Remove partial load after full store for high part access[PR71309]

Hi! On Tue, Jul 21, 2020 at 05:54:27AM -0500, Xiong Hu Luo wrote: > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > @@ -3,7 +3,7 @@ > > /* { dg-do compile { target { powerpc*-*-linux* } } } */ > /* { dg-r

Re: [PATCH] libgccjit: Handle truncation and extension for casts [PR 95498]

Hi Antoni, a couple of nits and some thoughts. Antoni Boucher via Gcc-patches writes: > 2020-07-12 Antoni Boucher > > gcc/jit/ > PR target/95498 > * jit-playback.c: Add support to handle truncation and extension ^^^ here we usually a

Re: [committed] libstdc++: Add std::from_chars for floating-point types

On Tue, 21 Jul 2020, Jonathan Wakely via Gcc-patches wrote: > I also noticed some strings give an underflow error with glibc's > strtod, but are valid for the Microsoft implementation. For example, > this one: > https://github.com/microsoft/STL/blob/master/tests/std/tests/P0067R5_charconv/double_f

Re: [PATCH] c++: Fixing the wording of () aggregate-init [PR92812]

On Tue, 21 Jul 2020 at 22:39, Marek Polacek wrote: > > Okay. I think it's remotely reasonable that a static_cast(42) would > > work for an array, then. > > And by a natural extension, that using the concrete type would also > > work. That seems consistent, > > but doesn't seem like it rises to the

c++: Fix scan forward over pragma [PR96257]

It turns out that the paren scanning code is used for speculatively searching to see if we're looking at a compound_literal. So we shouldn't always purge pragma tokens. gcc/cp/ * parser.c (cp_lexer_consume_token): Drop PRAGMA_EOL assert. (cp_parser_skip_to_c

Re: [PATCH] c++: Fixing the wording of () aggregate-init [PR92812]

On Tue, Jul 21, 2020 at 10:03:37PM +0300, Ville Voutilainen via Gcc-patches wrote: > On Tue, 21 Jul 2020 at 21:56, Marek Polacek wrote: > > > > On Tue, Jul 21, 2020 at 12:53:03PM +0300, Ville Voutilainen wrote: > > > On Tue, 21 Jul 2020 at 02:28, Marek Polacek wrote: > > > > > > > > P1975R0 twea

Re: **PING** [PATCH] PR fortran/89574 - [8/9/10/11 Regression] ICE in conv_function_val, at fortran/trans-expr.c:3792

Hi Harald, **ping** OK, that solution looks really good. Also, definetely worth backporting. Thanks a lot for the patch! Best regards Thomas

[PATCH] c++: decl_constant_value and unsharing [PR96197]

In the testcase from the PR we are seeing excessive memory use (> 5GB) during constexpr evaluation, almost all of which is due to the call to decl_constant_value in the VAR_DECL/CONST_DECL branch of cxx_eval_constant_expression. We reach here every time we evaluate an ARRAY_REF of a constexpr VAR_

**PING** [PATCH] PR fortran/89574 - [8/9/10/11 Regression] ICE in conv_function_val, at fortran/trans-expr.c:3792

**ping** > Gesendet: Dienstag, 14. Juli 2020 um 23:20 Uhr > Von: "Harald Anlauf" > An: "fortran" , "gcc-patches" > Betreff: [PATCH] PR fortran/89574 - [8/9/10/11 Regression] ICE in > conv_function_val, at fortran/trans-expr.c:3792 > > As Fortran allows to rename a symbol on use, we need to be c

Re: [PATCH] c++: Fixing the wording of () aggregate-init [PR92812]

On Tue, 21 Jul 2020 at 21:56, Marek Polacek wrote: > > On Tue, Jul 21, 2020 at 12:53:03PM +0300, Ville Voutilainen wrote: > > On Tue, 21 Jul 2020 at 02:28, Marek Polacek wrote: > > > > > > P1975R0 tweaks the static_cast wording: it says that "An expression e can > > > be > > > explicitly convert

Re: [PATCH] c++: Fixing the wording of () aggregate-init [PR92812]

On Tue, Jul 21, 2020 at 12:53:03PM +0300, Ville Voutilainen wrote: > On Tue, 21 Jul 2020 at 02:28, Marek Polacek wrote: > > > > P1975R0 tweaks the static_cast wording: it says that "An expression e can be > > explicitly converted to a type T if [...] T is an aggregate type having a > > first > >

[committed]: i386: Rename TARGET_USE_XCHG_FOR_ATOMIC_STORE to TARGET_AVOID_MFENCE.

The following is needed to synchronize the tuning flag, new in gcc-10, with the rename in gcc-11. The flag is now named "avoid_mfence" as this is what it really does. No other functional changes on gcc-10 branch, 2020-07-21 Uroš Bizjak gcc/ChangeLog: * config/i386/i386.h (TARGET_AVOID_MF

[PATCH 3/3] MSP430: Simplify and extend shift instruction patterns

The implementation of define_expand and define_insn patterns to handle shifts in the MSP430 backend is inconsistent, resulting in missed opportunities to make best use of the architecture's features. There's now a single define_expand used as the entry point for all valid shifts, and the decision

[PATCH 2/3] expmed: Fix possible use of NULL_RTX return value from emit_store_flag

MSP430 does not support have any store-flag instructions, so emit_store_flag can return NULL_RTX. Catch the NULL_RTX in expmed.c:expand_sdiv_pow2. Successfully regtested on trunk for x86_64-pc-linux-gnu and msp430-elf. Ok to apply? >From cb0f8219ac90229c0336281d73f511c107c877d3 Mon Sep 17 00:00:0

Re: [committed] i386: Use lock prefixed insn instead of MFENCE [PR95750]

On Tue, Jul 21, 2020 at 6:13 PM Uros Bizjak wrote: > > On Tue, Jul 21, 2020 at 5:46 PM Franz Sirl > wrote: > > I didn't bisect it, but I see a profiledbootstrap ICE that may be related: > > Ah, mfence_sse2 can be expanded from the __builtin_ia32_mfence > independently of tuning flags. I'm testin

[PATCH] libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCS

Complement commit b932f770f70d ("x86_64 frame unwind info"), SVN r46374, , and replace `-fexceptions -fnon-call-exceptions' with `-fasynchronous-unwind-tables' in LIB2_DIVMOD_FUNCS compilation flags so as to provide unwind tables for the

[PATCH 1/3] expr: Allow scalar_int_mode target mode when converting a constant

is_int_mode does not allow MODE_PARTIAL_INT modes, so convert_modes was not allowing a constant value to be converted to a MODE_PARTIAL_INT for use as operand 2 in patterns such as ashlpsi3. The constant had to be copied into a register before it could be used, but now can be used directly as an op

[PATCH 0/3] MSP430: Improve code-generation for shift instructions

The attached series of patches improve code-generation for MSP430 shift instructions. The first two patches are changes to generic areas of GCC, required for the 3rd patch to have the desired effect. Successfully regtested on trunk for x86_64-pc-linux-gnu (for the generic changes) and msp430-elf.

Re: [PATCH] config/debuginfod.m4: Use PKG_CHECK_MODULES

On Tue, Jul 21, 2020 at 11:20 AM Tom Tromey wrote: > > Simon> Since it's debuginfo.m4 that is using PKG_CHECK_MODULES, can you put > the include > Simon> of pkg.m4 in debuginfo.m4, instead of in {binutils,gdb}/configure.ac? > > Simon> Otherwise, from GDB's point of view I think it looks good, unl

Re: [PATCH 5/6 ver 5] rs6000, Add vector splat builtin support

On Tue, 2020-07-21 at 10:27 -0700, Carl Love wrote: > Patch didn't seem to come thru. - >From d2d534d7b4a0caf77d362094ca8e3b53559ce80f Mon Sep 17 00:00:00 2001 From: Carl Love Date: Wed, 27 May 2020 10:07:44 -0500 Subject: [PATCH 5/6] rs6000, Add vector s

PATCH 6/6 ver 5] rs6000 Add vector blend, permute builtin support

[PATCH 6/6] rs6000 Add vector blend, permute builtin support -- V5 fixes: Update ChangeLog gcc/config/rs6000/rs6000-c.c: Reworked else if ((fcode == P10_BUILTIN_VEC_XXEVAL)|| (fcode == P10_BUILTIN_VXXPERMX)) to make error printing more compa

[PATCH 5/6 ver 5] rs6000, Add vector splat builtin support

[PATCH 0/6 ver 5] ] Permute Class Operations

Segher: I fixed the comments to patch 5 in the series. Patch 6 has yet to be reviewed. I made all the minor changes to patches 1 to 4 that you and Will mentioned. Those patches were approved with the minor changes so I will not bother to repost them. I will just be reposting patches 5 and 6.

Re: [PATCH V3] Practical Improvement to libgcc Complex Divide

Ping On 7/1/2020 11:30 AM, Patrick McGehearty via Gcc-patches wrote: (Version 3) (Added in version 3) Support for half, float, extended, and long double precision has been added to the prior work for double precision. Since half precision is computed with float precision as per current libgcc

[committed] MSP430: Remove do_no_relax_short_jumps

do_not_relax_short_jumps is an old cludge from from when the Binutils linker could not relax BR to JMP and vice-versa when shuffling "either" sections between upper and lower memory. This has been fixed since at least Binutils 2.30. Successfully regtested on trunk for msp430-elf. Committed as obvi

[committed] MSP430: Define extendqipsi2

The SXT instruction extends the sign of the low byte of the operand through the entire PSImode register. SXTX.A can be used to sign extend the low byte of a memory operand through to the 19th bit. Bits 31:20 are cleared. Successfully regtested on trunk for msp430-elf. Committed as obvious. >From a

[committed] MSP430: Define NO_FUNCTION_CSE

Calling a constant function address costs the same number of clock cycles as calling an address stored in a register. However, in terms of instruction length, calling a constant address is more expensive. Set NO_FUNCTION_CSE to true, only when optimizing for speed. Committed the attached patch as

Re: [stage1][PATCH] Change semantics of -frecord-gcc-switches and add -frecord-gcc-switches-format.

PING^4. Our company is waiting for this patch to be committed to upstream. Thanks a lot. Qing > On Jun 16, 2020, at 7:49 AM, Martin Liška wrote: > > PING^3 > > On 6/2/20 11:16 AM, Martin Liška wrote: >> PING^2 >> On 5/15/20 11:58 AM, Martin Liška wrote: >>> We're in stage1: PING^1 >>> >>>

Re: [committed] i386: Use lock prefixed insn instead of MFENCE [PR95750]

On Tue, Jul 21, 2020 at 5:46 PM Franz Sirl wrote: > > Am 2020-07-20 um 20:39 schrieb Uros Bizjak via Gcc-patches: > > Currently, __atomic_thread_fence(seq_cst) on x86 and x86-64 generates > > mfence instruction. A dummy atomic instruction (a lock-prefixed instruction > > or xchg with a memory oper

Re: 答复: [PATCH PR95696] regrename creates overlapping register allocations for vliw

Zhongyunde writes: > Thanks for your review. > > First of all, this is an optimization. OK, good. >gcc do sms before reload, and here each insn use pseudo-register. After > reload, they are allocated hard-register, then the regrename pass try to > adjust the register number with def/use ch

Re: [PATCH 0/4] testsuite: Add markers for default_packed targets

On Mon, 20 July 2020 г. 19:31:02 EEST Dimitar Dimitrov wrote: > Hi, > > I'm sending a few minor testsuite updates to add markers for targets using > packed structures by default. From those targets, I tested AVR and PRU. I > don't have setup to test cris and m32c. > > I also tested x86_64 to ensu

Re: [Patch] OpenMP: Fixes for omp critical + hint

On Tue, Jul 21, 2020 at 05:43:00PM +0200, Tobias Burnus wrote: > --- a/gcc/c-family/c-omp.c > +++ b/gcc/c-family/c-omp.c > @@ -106,6 +106,18 @@ c_finish_omp_taskgroup (location_t loc, tree body, tree > clauses) > tree > c_finish_omp_critical (location_t loc, tree body, tree name, tree clauses) >

Re: [committed] i386: Use lock prefixed insn instead of MFENCE [PR95750]

Am 2020-07-20 um 20:39 schrieb Uros Bizjak via Gcc-patches: Currently, __atomic_thread_fence(seq_cst) on x86 and x86-64 generates mfence instruction. A dummy atomic instruction (a lock-prefixed instruction or xchg with a memory operand) would provide the same sequential consistency guarantees whi

Re: [Patch] OpenMP: Fixes for omp critical + hint

On 7/21/20 2:18 PM, Jakub Jelinek wrote: On Tue, Jul 21, 2020 at 02:05:36PM +0200, Tobias Burnus wrote: This code is both called by C and C++ – and for C++. And I would like to permit "hint(N)" where N is a template parameter. Hence, I added another: '&& TREE_CODE (OMP_CLAUSE_HINT_EXPR (clau

Re: [PATCH] dse: Remove partial load after full store for high part access[PR71309]

Xiong Hu Luo writes: > This patch could optimize (works for char/short/int/void*): > > 6: r119:TI=[r118:DI+0x10] > 7: [r118:DI]=r119:TI > 8: r121:DI=[r118:DI+0x8] > > => > > 6: r119:TI=[r118:DI+0x10] > 16: r122:DI=r119:TI#8 > > Final ASM will be as below without partial load after full store(stxv+

Re: [PATCH] config/debuginfod.m4: Use PKG_CHECK_MODULES

Simon> Since it's debuginfo.m4 that is using PKG_CHECK_MODULES, can you put the include Simon> of pkg.m4 in debuginfo.m4, instead of in {binutils,gdb}/configure.ac? Simon> Otherwise, from GDB's point of view I think it looks good, unless Simon> Tom has some things to add. I'm happy with it. Tha

aarch64: (GCC-9 Backport) New Straight Line Speculation (SLS) mitigation flags

Here we introduce the flags that will be used for straight line speculation. The new flag introduced is `-mharden-sls=`. This flag can take arguments of `none`, `all`, or a comma seperated list of one or more of `retbr` or `blr`. `none` indicates no special mitigation of the straight line speculat

aarch64: (GCC-9 Backport) Introduce SLS mitigation for RET and BR instructions

Instructions following RET or BR are not necessarily executed. In order to avoid speculation past RET and BR we can simply append a speculation barrier. Since these speculation barriers will not be architecturally executed, they are not expected to add a high performance penalty. The speculation

aarch64: (GCC-9 Backport) Mitigate SLS for BLR instruction

This patch introduces the mitigation for Straight Line Speculation past the BLR instruction. This mitigation replaces BLR instructions with a BL to a stub which uses a BR to jump to the original value. These function stubs are then appended with a speculation barrier to ensure no straight line sp

SLS Mitigation patches backported for GCC9

Hello, Eventually we will want to backport the SLS patches to older branches. When the GCC10 release is unfrozen we will work on getting the same patches already posted backported to that branch. The patches already posted on the mailing list apply cleanly to the current releases/gcc-10 branch.

Re: [PATCH] middle-end: Call get_constant_section with DECL not EXP.

On Tue, Jul 21, 2020 at 3:17 PM David Edelsohn wrote: > > On Tue, Jul 21, 2020 at 4:04 AM Richard Biener > wrote: > > > > On Fri, Jul 10, 2020 at 4:54 PM David Edelsohn wrote: > > > > > > On Fri, Jul 10, 2020 at 2:55 AM Richard Biener > > > wrote: > > > > > > > > On Thu, Jul 9, 2020 at 8:29 PM

Re: [PATCH] middle-end: Call get_constant_section with DECL not EXP.

On Tue, Jul 21, 2020 at 4:04 AM Richard Biener wrote: > > On Fri, Jul 10, 2020 at 4:54 PM David Edelsohn wrote: > > > > On Fri, Jul 10, 2020 at 2:55 AM Richard Biener > > wrote: > > > > > > On Thu, Jul 9, 2020 at 8:29 PM David Edelsohn wrote: > > > > > > > > output_constant_def_contents() can c

Re: [committed] testsuite: Add signal checking for signal related testcase in analyzer.

On Tue, 2020-07-21 at 14:28 +0800, Kito Cheng wrote: > - Verifed on RISC-V and x86. > > gcc/testsuite/ChangeLog: > > * gcc.dg/analyzer/signal-1.c: Add dg-require-effective-target > signal. > * gcc.dg/analyzer/signal-2.c: Ditto. > * gcc.dg/analyzer/signal-3.c: Ditto. >

Re: [PATCH] target: fix default value checking of x_str_align_functions in aarch64.c

"Hu, Jiangping" writes: >> If there isn't anywhere that handles zero in the way that the documentation >> implies (i.e. with -falign-loops=0 being equivalent to -falign-loops) then >> maybe >> we should instead change the documentation to match the actual behaviour. >> > Yes, I confirmed in sourc

Re: [Patch] OpenMP: Fixes for omp critical + hint

On Tue, Jul 21, 2020 at 02:05:36PM +0200, Tobias Burnus wrote: > This code is both called by C and C++ – and for C++. And I would like > to permit "hint(N)" where N is a template parameter. > > Hence, I added another: > '&& TREE_CODE (OMP_CLAUSE_HINT_EXPR (clauses)) == INTEGER_CST' > to your pro

Re: [Patch] OpenMP: Fixes for omp critical + hint

On 7/21/20 1:25 PM, Jakub Jelinek via Fortran wrote: c_finish_omp_critical (location_t loc, tree body, tree name, tree clauses) { + gcc_assert (!clauses || OMP_CLAUSE_CODE (clauses) == OMP_CLAUSE_HINT); + if (name == NULL_TREE && clauses != NULL_TREE + && INTEGRAL_TYPE_P (TREE_TYPE (O

Re: [Patch] OpenMP: Fixes for omp critical + hint

On Tue, Jul 21, 2020 at 01:11:31PM +0200, Tobias Burnus wrote: > --- a/gcc/c-family/c-omp.c > +++ b/gcc/c-family/c-omp.c > @@ -106,6 +106,18 @@ c_finish_omp_taskgroup (location_t loc, tree body, tree > clauses) > tree > c_finish_omp_critical (location_t loc, tree body, tree name, tree clauses) >

[Patch] OpenMP: Fixes for omp critical + hint

Changes: * OpenMP requires a name with the hint clause, but not if the expression evaluates to zero == omp_sync_hint_none. The "but" was not implemented. * C++ lacked some of the C checks * I added a >= 0 check; permitted values are between 0 and 10 plus some '|' or '+' combinations, hence,

RE: [PATCH] target: fix default value checking of x_str_align_functions in aarch64.c

> Sorry for the slow response on this. Like you say, it seems to be a pretty > pervasive problem. In fact I couldn't see anywhere that actually treated - > falign-foo=0 as anything other than -falign-foo=1. > > Technically using an alignment of one for zero is within what the > documentation all

Re: [committed] libstdc++: Add std::from_chars for floating-point types

On 21/07/20 07:56 +0200, Florian Weimer wrote: * Jonathan Wakely via Libstdc: By replacing the use of strtod we could avoid allocation, avoid changing locale, and use optimised code paths specific to each std::chars_format case. We would also get more portable behaviour, rather than depending o

[PATCH] dse: Remove partial load after full store for high part access[PR71309]

This patch could optimize (works for char/short/int/void*): 6: r119:TI=[r118:DI+0x10] 7: [r118:DI]=r119:TI 8: r121:DI=[r118:DI+0x8] => 6: r119:TI=[r118:DI+0x10] 16: r122:DI=r119:TI#8 Final ASM will be as below without partial load after full store(stxv+ld): ld 10,16(3) mr 9,3 ld 3,24(3)

Re: [PATCH] c++: Fixing the wording of () aggregate-init [PR92812]

On Tue, 21 Jul 2020 at 02:28, Marek Polacek wrote: > > P1975R0 tweaks the static_cast wording: it says that "An expression e can be > explicitly converted to a type T if [...] T is an aggregate type having a > first > element x and there is an implicit conversion sequence from e to the type of >

Re: [PATCH][GCC][aarch64] Generation of adjusted ldp/stp for vector types

Richard Sandiford writes: > Yeah, that's certainly true for code in the compiler itself. Tests > kind-of get a pass stylewise though. It would be bad if everything in > the testsuite used GNU style, since then we'd never test anything else. ;-) LOL, good to know thanks Andrea

Re: [PATCH][GCC][aarch64] Generation of adjusted ldp/stp for vector types

Andrea Corallo writes: > Przemyslaw Wirkus writes: > >> diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_vec_v2sf.c >> b/gcc/testsuite/gcc.target/aarch64/ldp_vec_v2sf.c >> new file mode 100644 >> index >> ..fbdae1c6cff1aef40db644361381ce511f0be64a >> ---

Re: [PATCH][GCC][aarch64] Generation of adjusted ldp/stp for vector types

Przemyslaw Wirkus writes: > diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_vec_v2sf.c > b/gcc/testsuite/gcc.target/aarch64/ldp_vec_v2sf.c > new file mode 100644 > index > ..fbdae1c6cff1aef40db644361381ce511f0be64a > --- /dev/null > +++ b/gcc/testsuite/

RE: [PATCH][GCC][aarch64] Generation of adjusted ldp/stp for vector types

Richard, In attachment reworked patch. > -Original Message- > From: Richard Sandiford > Sent: 13 July 2020 17:13 > To: Przemyslaw Wirkus > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Marcus Shawcroft > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC][aarch64] Generation of adjusted ld

Re: [PATCH v2] [RISC-V] Add support for TLS stack protector canary access

Hi Cooper: Could you add testcases like ppc[3-4]? [3] https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/powerpc/ssp-1.c [4] https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/powerpc/ssp-2.c On Mon, Jul 20, 2020 at 10:04 AM cooper via Gcc-patches wrote

Re: [PATCH] middle-end: Call get_constant_section with DECL not EXP.

On Fri, Jul 10, 2020 at 4:54 PM David Edelsohn wrote: > > On Fri, Jul 10, 2020 at 2:55 AM Richard Biener > wrote: > > > > On Thu, Jul 9, 2020 at 8:29 PM David Edelsohn wrote: > > > > > > output_constant_def_contents() can call get_constant_section() with an > > > EXP that is a CONSTRUCTOR, which

Re: [PATCH] vect: Support vector with length cost modeling

On Tue, Jul 21, 2020 at 7:52 AM Kewen.Lin wrote: > > Hi, > > This patch is to add the cost modeling for vector with length, > it mainly follows what we generate for vector with length in > functions vect_set_loop_controls_directly and vect_gen_len > at the worst case. > > For Power, the length is

Re: [PATCH] Add TARGET_LOWER_LOCAL_DECL_ALIGNMENT [PR95237]

On Tue, Jul 21, 2020 at 7:16 AM Sunil Pandey wrote: > > On Mon, Jul 20, 2020 at 5:06 AM Richard Biener > wrote: > > > > On Sat, Jul 18, 2020 at 7:57 AM Sunil Pandey wrote: > > > > > > On Fri, Jul 17, 2020 at 1:22 AM Richard Biener > > > wrote: > > > > > > > > On Fri, Jul 17, 2020 at 7:15 AM Sun

Re: [patch] gcc/testsuite: Scale down long-running tree-prof.exp tests on slow targets

On Tue, Jul 21, 2020 at 1:14 AM Sandra Loosemore wrote: > > On 7/20/20 2:15 AM, Richard Biener wrote: > > > I think at least parts of tree-prof.exp exercises sample-based profiling > > which might require more iterations. For example cold_partition_label.c > > was changed by > > > > commit f63ba7

[PATCH] testsuite: Improve signal supporting detection

gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_signal): Check signal supporting by checking signal.h, signal and raise is available. --- gcc/testsuite/lib/target-supports.exp | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/

答复: [PATCH PR95696] regrename creates overlapping register allocations for vliw

Thanks for your review. First of all, this is an optimization. gcc do sms before reload, and here each insn use pseudo-register. After reload, they are allocated hard-register, then the regrename pass try to adjust the register number with def/use chain created by build_def_use. As now gcc d