(resending from a different account, as emails seem to do not
go out from my other account at this time)
Am Montag, den 02.08.2021, 16:05 +0200 schrieb Martin Uecker:
> > On Sun, Aug 1, 2021 at 7:37 PM Uecker, Martin
> > wrote:
> > >
> > >
> > > Here is an attempt to fix some old and
PR target/80566
* g++.target/i386/pr80566-1.C: New test.
* g++.target/i386/pr80566-2.C: Likewise.
---
gcc/testsuite/g++.target/i386/pr80566-1.C | 15 +++
gcc/testsuite/g++.target/i386/pr80566-2.C | 14 ++
2 files changed, 29 insertions(+)
create
On Tue, Aug 3, 2021 at 3:34 AM Joseph Myers wrote:
>
> On Mon, 2 Aug 2021, liuhongt via Gcc-patches wrote:
>
> > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > index 7979e240426..dc673c89bc8 100644
> > --- a/gcc/config/i386/i386.c
> > +++ b/gcc/config/i386/i386.c
> > @@ -23352,6
On Tue, Aug 3, 2021 at 1:48 AM H.J. Lu via Gcc-patches
wrote:
>
> In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
> if possible.
>
> gcc/
>
> * config/i386/i386.c (ix86_gen_scratch_sse_rtx): In 64-bit mode,
> try XMM31 to avoid vzeroupper.
LGTM.
>
>
On Mon, Aug 2, 2021 at 6:20 PM Richard Biener via Gcc-patches
wrote:
>
> On Mon, Aug 2, 2021 at 6:33 AM liuhongt wrote:
> >
> > Hi:
> > This patch supports cond_add/sub/mul/div expanders for vector
> > float/double.
> > There're still cond_fma/fms/fnms/fma/max/min/xor/ior/and left which I
On Mon, Aug 02, 2021 at 08:31:43AM -0500, Bill Schmidt wrote:
> Interestingly, when the quadword compares are expanded at GIMPLE time,
> we generate worse code involving individual 64-bit compares. For the
> time being, I will not expand these at GIMPLE time; independently, this
> bears
Hi!
On Thu, Jul 15, 2021 at 06:29:18PM -0500, Paul A. Clarke wrote:
> Copy the test for _mm_minpos_epu16 from
> gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c, with
> a few adjustments:
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-phminposuw.c
> @@ -0,0 +1,68 @@
> +/* {
The upcoming Go 1.17 release has a new language feature: it permits
conversions from slice types to pointer-to-array types. If the slice
is too short, the conversion panics. This patch implements this new
feature in gccgo. Bootstrapped and ran Go testsuite on
x86_64-pc-linux-gnu. Committed to
Hi!
On Thu, Jul 15, 2021 at 06:29:17PM -0500, Paul A. Clarke wrote:
> Add a naive implementation of the subject x86 intrinsic to
> ease porting.
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -172,4 +172,31 @@ _mm_test_mix_ones_zeros (__m128i __A, __m128i
The upcoming Go 1.17 release adds two new functions to the unsafe
package: unsafe.Add and unsafe.Slice. These functions must be
implemented in the compiler. This patch implements them for gccgo.
Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
to mainline.
Ian
The write_only mode to attribute access specifies that the pointer
applies to is used to write to the referenced object but not read
from it.
A function that uses the pointer to read the referenced object might
rely on the contents of uninitialized memory and so such attempts
should be
> On Aug 2, 2021, at 5:09 PM, Eric Gallager wrote:
>
> On Wed, Jul 28, 2021 at 11:36 PM Matt Jacobson via Gcc-patches
> wrote:
>>
>> As is, an invocation of GCC with -fnext-runtime -fobjc-abi-version=2 crashes,
>> unless target-specific code adds an implicit -fno-objc-sjlj-exceptions (which
On Wed, Jul 28, 2021 at 11:36 PM Matt Jacobson via Gcc-patches
wrote:
>
> As is, an invocation of GCC with -fnext-runtime -fobjc-abi-version=2 crashes,
> unless target-specific code adds an implicit -fno-objc-sjlj-exceptions (which
> Darwin does).
>
> This patch makes the general case not crash.
Enable store fusion on Power10.
Use the SCHED_REORDER hook to implement Power10 specific ready list reordering.
As of now, pairing stores for store fusion is the only function being
performed.
Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
master?
-Pat
2021-08-02
On Mon, 2 Aug 2021, liuhongt via Gcc-patches wrote:
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 7979e240426..dc673c89bc8 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -23352,6 +23352,8 @@ ix86_get_excess_precision (enum excess_precision_type
In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
if possible.
gcc/
* config/i386/i386.c (ix86_gen_scratch_sse_rtx): In 64-bit mode,
try XMM31 to avoid vzeroupper.
gcc/testsuite/
* gcc.target/i386/avx-vzeroupper-14.c: Pass -mno-avx512f to
On 8/2/21 3:07 PM, Eric Botcazou wrote:
>> It was pointed out in PR101598 to be inappropriate, that
>> ignored Ada decls receive the source line number which was
>> recorded in the function decl's DECL_SOURCE_LOCATION.
>> Therefore set all front-end-generated Ada decls with
>> DECL_IGNORED_P to
On Mon, Aug 2, 2021 at 4:57 PM H.J. Lu wrote:
>
> On Mon, Aug 2, 2021 at 4:20 AM Uros Bizjak wrote:
> >
> > On Fri, Jul 30, 2021 at 11:32 PM H.J. Lu wrote:
> > >
> > > We can use TImode/OImode/XImode integers for piecewise move and store.
> > >
> > > 1. Define MAX_MOVE_MAX to 64, which is the
On 30/07/21 18:13 +0100, Jonathan Wakely wrote:
This adds a configure check for the GNU extension secure_getenv and then
uses it for looking up TMPDIR and similar variables.
Signed-off-by: Jonathan Wakely
libstdc++-v3/ChangeLog:
PR libstdc++/65018
* configure.ac: Check for
When the comparison with a nullptr_t is ill-formed, there is an
additional error for C++11 mode due to the constexpr function body being
invalid.
Signed-off-by: Jonathan Wakely
libstdc++-v3/ChangeLog:
* testsuite/20_util/tuple/comparison_operators/overloaded2.cc:
Add dg-error
This was meant to be an internal construct, but I see folks are using
it and submitting PRs against it. Let's just remove this to avoid
further confusion.
Tested on x86-64 Linux.
Pushed to keep PRs down and Jeff happy :).
gcc/ChangeLog:
PR tree-optimization/101724
*
On Mon, Aug 2, 2021 at 4:20 AM Uros Bizjak wrote:
>
> On Fri, Jul 30, 2021 at 11:32 PM H.J. Lu wrote:
> >
> > We can use TImode/OImode/XImode integers for piecewise move and store.
> >
> > 1. Define MAX_MOVE_MAX to 64, which is the constant maximum number of
> > bytes that a single instruction
A change to the way gas interprets the .fpu directive in binutils-2.34
means that issuing .fpu will clear any features set by .arch_extension
that apply to the floating point or simd units. This unfortunately
causes problems for more recent versions of the architecture because
we currently emit
arm_configure_build_target is usually used to reconfigure the
arm_active_target structure, which is then used to reconfigure a
number of other global variables describing the current target.
Occasionally, however, we need to use arm_configure_build_target to
construct a temporary target structure
This should never happen now if GCC is invoked by the driver, but in
the unusual case of calling cc1 (or its ilk) directly from the command
line the build target's arch_name string can remain NULL. This can
complicate later processing meaning that we need to check for this
case explicitly in
This patch series addresses an issue that has come to light due to a
change in the way GAS handles .fpu directives in the assembler. A fix
to the assembler made in binutils 2.34 to clear out all features
realated to the FPU when .fpu is emitted has started causing problems
for GCC because of the
This teaches forwprop to rewrite more vector loads that are only
used in BIT_FIELD_REFs as scalar loads. This provides the
remaining uplift to SPEC CPU 2017 510.parest_r on Zen 2 which
has CPU gathers disabled.
In particular vector load + vec_unpack + bit-field-ref is turned
into (extending)
This adds a gather vectorization capability to the vectorizer
without target support by decomposing the offset vector, doing
sclar loads and then building a vector from the result. This
is aimed mainly at cases where vectorizing the rest of the loop
offsets the cost of vectorizing the gather.
Hi Will,
On 7/29/21 7:42 AM, Bill Schmidt wrote:
On 7/28/21 4:21 PM, will schmidt wrote:
On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
+/* Vector compares; EQ, NE, GE, GT, LE. */
+case RS6000_BIF_VCMPEQUB:
+case RS6000_BIF_VCMPEQUH:
+case
On Fri, 30 Jul 2021, Bernd Edlinger wrote:
>
>
> On 7/29/21 9:23 AM, Richard Biener wrote:
> > On Wed, 28 Jul 2021, Bernd Edlinger wrote:
> >
> >> On 7/28/21 2:51 PM, Richard Biener wrote:
> >>> On Mon, 26 Jul 2021, Bernd Edlinger wrote:
> >>>
> Ignored functions decls that are compiled
This is the right patch. The previous one is missing noexcept. Sorry.
On Mon, Aug 2, 2021 at 9:23 AM Maged Michael
wrote:
> Please find attached an updated patch after incorporating Jonathan's
> suggestions.
>
> Changes from the last patch include:
> - Add a TSAN macro to bits/c++config.
> -
Please find attached an updated patch after incorporating Jonathan's
suggestions.
Changes from the last patch include:
- Add a TSAN macro to bits/c++config.
- Use separate constexpr bool-s for the conditions for lock-freedom,
double-width and alignment.
- Move the code in the optimized path to a
On 2021/7/23 6:39 PM, Jakub Jelinek wrote:
On Fri, Jul 23, 2021 at 06:21:41PM +0800, Chung-Lin Tang wrote:
--- a/libgomp/icv-device.c
+++ b/libgomp/icv-device.c
@@ -61,8 +61,17 @@ omp_is_initial_device (void)
return 1;
}
+int
+omp_get_device_num (void)
+{
+ /* By specification, this
On 2021/7/23 7:01 PM, Tobias Burnus wrote:
I personally prefer having:
int initial_dev;
and inside 'omp target' (with 'map(from:initial_dev)'):
initial_device = omp_is_initial_device();
Then the check would be:
if (initial_device && host_device_num != device_num)
abort();
> It was pointed out in PR101598 to be inappropriate, that
> ignored Ada decls receive the source line number which was
> recorded in the function decl's DECL_SOURCE_LOCATION.
> Therefore set all front-end-generated Ada decls with
> DECL_IGNORED_P to UNKNOWN_LOCATION.
>
> 2021-07-24 Bernd
On Mon, Aug 2, 2021 at 1:31 PM Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Mon, Aug 2, 2021 at 12:43 PM Richard Sandiford
> > wrote:
> >>
> >> Richard Biener via Gcc-patches writes:
> >> > On Fri, Jul 30, 2021 at 5:59 PM Richard Sandiford via Gcc-patches
> >> > wrote:
> >> >>
>
Richard Biener writes:
> On Mon, Aug 2, 2021 at 12:43 PM Richard Sandiford
> wrote:
>>
>> Richard Biener via Gcc-patches writes:
>> > On Fri, Jul 30, 2021 at 5:59 PM Richard Sandiford via Gcc-patches
>> > wrote:
>> >>
>> >> This patch adds a simple class for holding A/B fractions.
>> >> As the
On Fri, Jul 30, 2021 at 11:32 PM H.J. Lu wrote:
>
> We can use TImode/OImode/XImode integers for piecewise move and store.
>
> 1. Define MAX_MOVE_MAX to 64, which is the constant maximum number of
> bytes that a single instruction can move quickly between memory and
> registers or between two
On Mon, Aug 2, 2021 at 12:43 PM Richard Sandiford
wrote:
>
> Richard Biener via Gcc-patches writes:
> > On Fri, Jul 30, 2021 at 5:59 PM Richard Sandiford via Gcc-patches
> > wrote:
> >>
> >> This patch adds a simple class for holding A/B fractions.
> >> As the comments in the patch say, the
Richard Biener via Gcc-patches writes:
> On Fri, Jul 30, 2021 at 5:59 PM Richard Sandiford via Gcc-patches
> wrote:
>>
>> This patch adds a simple class for holding A/B fractions.
>> As the comments in the patch say, the class isn't designed
>> to have nice numerial properties at the extremes.
On Mon, Aug 2, 2021 at 6:33 AM liuhongt wrote:
>
> Hi:
> This patch supports cond_add/sub/mul/div expanders for vector float/double.
> There're still cond_fma/fms/fnms/fma/max/min/xor/ior/and left which I
> failed to figure out a testcase to validate them.
> Also cond_add/sub/mul for vector
On Sun, Aug 1, 2021 at 7:37 PM Uecker, Martin
wrote:
>
>
>
> Here is an attempt to fix some old and annoying bugs related
> to VLAs and statement expressions. In particulary, this seems
> to fix the issues with variably-modified types which are
> returned from statement expressions (which works
On Sat, Jul 31, 2021 at 9:56 AM Roger Sayle wrote:
>
>
> Many thanks again to Jakub Jelinek for a speedy fix for PR 101642.
> Interestingly, that test case "bswap16(x) ? : x" also reveals a
> missed optimization opportunity. The resulting "x ? bswap(x) : 0"
> can be further simplified to just
On Fri, Jul 30, 2021 at 9:22 PM apinski--- via Gcc-patches
wrote:
>
> From: Andrew Pinski
>
> Just like the old bug PR9651, unsigned_fix rtl should
> also be handled as a trapping instruction.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
OK.
> gcc/ChangeLog:
>
>
On Fri, Jul 30, 2021 at 9:09 AM Eugene Rozenfeld via Gcc-patches
wrote:
>
> This patch has the following changes:
>
> 1. The main fix is in auto-profile.c: the histogram value for
>indirect calls was incorrectly set up. That is fixed now.
>
> 2. Several tests now have
On Fri, Jul 30, 2021 at 5:59 PM Richard Sandiford via Gcc-patches
wrote:
>
> This patch adds a simple class for holding A/B fractions.
> As the comments in the patch say, the class isn't designed
> to have nice numerial properties at the extremes.
>
> The motivating use case was some aarch64
On Fri, Jul 30, 2021 at 1:15 PM Kewen.Lin wrote:
>
> Hi,
>
> This patch is to fix the typos in the move_sese_region_to_fn.
> As mentioned here [1], I tried to debug the test case
> gcc.dg/graphite/pr83359.c with trunk, but I found it didn't
> go into the hunk guard with "if
on 2021/8/2 下午5:11, Richard Biener wrote:
> On Mon, 2 Aug 2021, Kewen.Lin wrote:
>
>> on 2021/8/2 下午3:09, Richard Biener wrote:
>>> On Mon, 2 Aug 2021, Kewen.Lin wrote:
>>>
on 2021/7/30 下午10:04, Kewen.Lin via Gcc-patches wrote:
> Hi Richi,
>
> on 2021/7/30 下午7:34, Richard Biener
On Mon, 2 Aug 2021, Kewen.Lin wrote:
> on 2021/8/2 下午3:09, Richard Biener wrote:
> > On Mon, 2 Aug 2021, Kewen.Lin wrote:
> >
> >> on 2021/7/30 下午10:04, Kewen.Lin via Gcc-patches wrote:
> >>> Hi Richi,
> >>>
> >>> on 2021/7/30 下午7:34, Richard Biener wrote:
> This adds a gather vectorization
on 2021/8/2 下午3:09, Richard Biener wrote:
> On Mon, 2 Aug 2021, Kewen.Lin wrote:
>
>> on 2021/7/30 下午10:04, Kewen.Lin via Gcc-patches wrote:
>>> Hi Richi,
>>>
>>> on 2021/7/30 下午7:34, Richard Biener wrote:
This adds a gather vectorization capability to the vectorizer
without target
Richard Biener writes:
> On Mon, 2 Aug 2021, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Fri, 30 Jul 2021, Richard Sandiford wrote:
>> >> > @@ -9456,6 +9499,51 @@ vectorizable_load (vec_info *vinfo,
>> >> > data_ref = NULL_TREE;
>> >> >
On Mon, 2 Aug 2021, Richard Sandiford wrote:
> Richard Biener writes:
> > On Fri, 30 Jul 2021, Richard Sandiford wrote:
> >> > @@ -9456,6 +9499,51 @@ vectorizable_load (vec_info *vinfo,
> >> > data_ref = NULL_TREE;
> >> > break;
> >> >
Richard Biener writes:
> On Fri, 30 Jul 2021, Richard Sandiford wrote:
>> > @@ -9456,6 +9499,51 @@ vectorizable_load (vec_info *vinfo,
>> >data_ref = NULL_TREE;
>> >break;
>> > }
>> > + else if (memory_access_type ==
On Fri, 30 Jul 2021, Richard Sandiford wrote:
> Richard Biener writes:
> > This adds a gather vectorization capability to the vectorizer
> > without target support by decomposing the offset vector, doing
> > sclar loads and then building a vector from the result. This
> > is aimed mainly at
On Mon, 2 Aug 2021, Kewen.Lin wrote:
> on 2021/7/30 下午10:04, Kewen.Lin via Gcc-patches wrote:
> > Hi Richi,
> >
> > on 2021/7/30 下午7:34, Richard Biener wrote:
> >> This adds a gather vectorization capability to the vectorizer
> >> without target support by decomposing the offset vector, doing
>
From: "Guo, Xuepeng"
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect FEATURE_AVX512FP16.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX512FP16_SET,
OPTION_MASK_ISA_AVX512FP16_UNSET,
On Fri, 30 Jul 2021, Tom de Vries wrote:
> On 7/30/21 6:17 PM, Martin Sebor wrote:
> > On 7/28/21 9:20 AM, Tom de Vries wrote:
> >> Hi,
> >>
> >> Improve nonnull attribute documentation in a number of ways:
> >>
> >> Reorganize discussion of effects into:
> >> - effects for calls to functions
On Fri, 30 Jul 2021, Martin Sebor wrote:
> On 7/30/21 2:21 PM, Tom de Vries wrote:
> > On 7/30/21 6:17 PM, Martin Sebor wrote:
> >> On 7/28/21 9:20 AM, Tom de Vries wrote:
> >>> Hi,
> >>>
> >>> Improve nonnull attribute documentation in a number of ways:
> >>>
> >>> Reorganize discussion of
gcc/ChangeLog:
* config/i386/avx512fp16intrin.h (_mm_set_ph): New intrinsic.
(_mm256_set_ph): Likewise.
(_mm512_set_ph): Likewise.
(_mm_setr_ph): Likewise.
(_mm256_setr_ph): Likewise.
(_mm512_setr_ph): Likewise.
(_mm_set1_ph): Likewise.
libgcc/ChangeLog:
* config/i386/32/sfp-machine.h (_FP_NANFRAC_H): New macro.
* config/i386/64/sfp-machine.h (_FP_NANFRAC_H): Ditto.
* config/i386/sfp-machine.h (_FP_NANSIGN_H): Ditto.
* config/i386/t-softfp: Add hf soft-fp.
* config.host: Add
libgcc/ChangeLog
* soft-fp/eqhf2.c: New file.
* soft-fp/extendhfdf2.c: New file.
* soft-fp/extendhfsf2.c: New file.
* soft-fp/extendhfxf2.c: New file.
* soft-fp/half.h (FP_CMP_EQ_H): New marco.
* soft-fp/truncdfhf2.c: New file
*
gcc/ada/ChangeLog:
* gcc-interface/misc.c (gnat_post_options): Issue an error for
-fexcess-precision=16.
gcc/c-family/ChangeLog:
* c-common.c (excess_precision_mode_join): Update below comments.
(c_ts18661_flt_eval_method): Set excess_precision_type to
Update from v2:
1. Support -fexcess-precision=16 which will enable
FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 when backend supports _Float16.
2. Update ix86_get_excess_precision, so -fexcess-precision=standard
should not do anything different from -fexcess-precision=fast
regarding _Float16.
3. Avoiding
gcc/ChangeLog:
* config/i386/i386-modes.def (FLOAT_MODE): Define ieee HFmode.
* config/i386/i386.c (enum x86_64_reg_class): Add
X86_64_SSEHF_CLASS.
(merge_classes): Handle X86_64_SSEHF_CLASS.
(examine_argument): Ditto.
(construct_container): Ditto.
on 2021/7/30 下午10:04, Kewen.Lin via Gcc-patches wrote:
> Hi Richi,
>
> on 2021/7/30 下午7:34, Richard Biener wrote:
>> This adds a gather vectorization capability to the vectorizer
>> without target support by decomposing the offset vector, doing
>> sclar loads and then building a vector from the
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