On Thu, Jul 1, 2021 at 2:17 PM liuhongt wrote:
>
> From: "H.J. Lu"
>
> gcc/ChangeLog:
>
> * config/i386/i386-expand.c
> (ix86_avx256_split_vector_move_misalign): Handle V16HF mode.
> * config/i386/i386.c
> (ix86_preferred_simd_mode): Handle HF mode.
> * con
This changes the default debug format for Alpha/VMS to DWARF2 only,
skipping emission of VMS debug info which is going do be deprecated
for GCC 12 alongside the support for STABS.
It looks like other flavors of VMS never used VMS_DEBUG by default
but only the alpha port did.
I have no good means
This removes the fallback to STABS as default for cygwin and mingw
when the assembler does not support .secrel32 and the default is
to emit 32bit code. Support for .secrel32 was added to binutils 2.16
released in 2005 so instead document that as requirement.
I left the now unused check for .secre
This removes the --with-stabs configure option which had no effect
since quite some time.
Will push when it was included in some bootstrap/regtest cycle.
2021-09-10 Richard Biener
* configure.ac (--with-stabs): Remove.
* configure: Regenerate.
* doc/install.texi: Remov
On Thu, 9 Sep 2021, Jeff Law wrote:
>
>
> On 9/9/2021 7:19 AM, Richard Biener via Gcc-patches wrote:
> > The following removes the unused config/dbx.h file and removes the
> > setting of PREFERRED_DEBUGGING_TYPE from dbxcoff.h which is
> > overridden by all users (djgpp/mingw/cygwin) via either
Bill,
Thanks so much for your advice.
I refined the patch and passed the bootstrap and regression test.
Just one thing, the test case becomes unsupported on P9 if I set "{
dg-require-effective-target power10_ok }". I just want the test case to
be compiled and check its assembly. Do we nee
On Thu, Sep 9, 2021 at 4:00 PM Hongtao Liu wrote:
>
> On Thu, Sep 9, 2021 at 3:54 PM liuhongt wrote:
> >
> > Hi:
> > As a follow up of [1], the patch removes all scalar mode copysign related
> > post_reload splitter/define_insn and expand copysign directly into below
> > using
> > paradoxical
Hi:
In general_operand, paradoxical subregs w/ outermode SCALAR_FLOAT_MODE_P
are not allowed unless lra_in_progress, so this patch add the restriction
to validate_subreg as well.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,}
Also the newly added tests are compiled with aarch64-linu
Currently for (vec_concat:M (vec_select op0 idx1)(vec_select op0 idx2)),
optimizer wouldn't simplify if op0 has different mode with M, but that's too
restrict which will prevent below optimization, the condition can be relaxed
to op0 must have same inner mode with M.
(set (reg:V2DF 87 [ xx ])
on 2021/9/10 上午11:22, Kewen.Lin via Gcc-patches wrote:
> Hi Segher and Bill,
>
> Thanks a lot for your reviews and helps!
>
> on 2021/9/10 上午1:19, Bill Schmidt wrote:
>> On 9/9/21 11:11 AM, Segher Boessenkool wrote:
>>> Hi!
>>>
>>> On Wed, Sep 08, 2021 at 02:57:14PM +0800, Kewen.Lin wrote:
>>
Hi Segher and Bill,
Thanks a lot for your reviews and helps!
on 2021/9/10 上午1:19, Bill Schmidt wrote:
> On 9/9/21 11:11 AM, Segher Boessenkool wrote:
>> Hi!
>>
>> On Wed, Sep 08, 2021 at 02:57:14PM +0800, Kewen.Lin wrote:
> + /* If we have strided or elementwise loads into a vector, it's
On Fri, Sep 10, 2021 at 7:49 AM Segher Boessenkool
wrote:
>
> On Thu, Sep 09, 2021 at 08:16:16AM +0200, Richard Biener wrote:
> > > I think we should (longer term) get rid of the overloaded meanings and
> > > uses of subregs. One fairly simple thing is to make a new rtx code
> > > "bit_cast" (or
On Linux/x86_64,
a25e0b5e6ac8a77a71c229e0a7b744603365b0e9 is the first bad commit
commit a25e0b5e6ac8a77a71c229e0a7b744603365b0e9
Author: qing zhao
Date: Thu Sep 9 15:44:49 2021 -0700
Add -ftrivial-auto-var-init option and uninitialized variable attribute.
caused
FAIL: c-c++-common/auto-
On Thu, Sep 9, 2021 at 11:31 PM H.J. Lu wrote:
>
> On Wed, Jul 21, 2021 at 12:44 AM liuhongt wrote:
> >
> > From: "H.J. Lu"
> >
> > Copied from regular XMM ABI tests. Only run AVX512FP16 ABI tests for ELF
> > targets.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/x86_64/abi/avx51
On Thu, Sep 09, 2021 at 08:16:16AM +0200, Richard Biener wrote:
> > I think we should (longer term) get rid of the overloaded meanings and
> > uses of subregs. One fairly simple thing is to make a new rtx code
> > "bit_cast" (or is there a nice short more traditional name for it?)
>
> But subreg
On Thu, Sep 09, 2021 at 10:49:11PM +, Qing Zhao wrote:
> Hi, FYI
>
> I just committed the following patch to gcc upstream:
>
>
> https://gcc.gnu.org/pipermail/gcc-cvs/2021-September/353195.html
Hurray! Thank you so much for working on this, and thanks also to the
reviewers and everyone else
On Thu, Sep 09, 2021 at 08:16:16AM +0200, Richard Biener wrote:
> But subreg _is_ bit_cast. What is odd to me is that a "disallowed" subreg
> like (subreg:SF (reg:TI ..) 0) magically becomes valid (in terms of
> validate_subreg) if you rewrite it as (subreg:SF (subreg:SI (reg:TI ..) 0) 0).
> Of co
Hi, FYI
I just committed the following patch to gcc upstream:
https://gcc.gnu.org/pipermail/gcc-cvs/2021-September/353195.html
Thanks.
Qing
> On Sep 6, 2021, at 5:16 AM, Richard Biener wrote:
>
> On Sat, 21 Aug 2021, Qing Zhao wrote:
>
>> Hi,
>>
>> This is the 8th version of the patch fo
Hi David.
> The output templates for zero_extendhidi2 and zero_extendqidi2 could
> lead to incorrect code generation when zero-extending one register into
> another. This patch adds a new output template to the define_insns to
> handle such cases and produce correct asm.
>
> gcc/ChangeLog:
>
On Tue, Sep 7, 2021 at 12:12 AM Michael Meissner via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> This patch fixes the breakage in the PowerPC due to a recent change in
> SUBREG
> behavior. While it is arguable that the patch that caused the breakage
> should
> be reverted, this patch should b
New instructions have been added over time to the eBPF ISA, but
previously there has been no good method to select which version to
target in GCC.
This patch adds the following options to the BPF backend:
-mcpu={v1, v2, v3}
Select which version of the eBPF ISA to target. This enables or
This commit adds tests for the new -mjmpext, -mjmp32 and -malu32 feature
options in the BPF backend.
gcc/testsuite/ChangeLog:
* gcc.target/bpf/alu-1.c: New test.
* gcc.target/bpf/jmp-1.c: New test.
---
gcc/testsuite/gcc.target/bpf/alu-1.c | 56 +++
gcc/test
This commit adds documentation for the new BPF options -mcpu, -mjmpext,
-mjmp32, and -malu32.
gcc/ChangeLog:
* doc/invoke.texi: Document BPF -mcpu, -mjmpext, -mjmp32 and -malu32
options.
---
gcc/doc/invoke.texi | 39 ++-
1 file changed, 38 inser
New instructions have been added over time to the eBPF ISA, but
previously there has been no good method to select which version to
target in GCC.
This patch adds the following options to the BPF backend:
-mcpu={v1, v2, v3}
Select which version of the eBPF ISA to target. This enables or
The output templates for zero_extendhidi2 and zero_extendqidi2 could
lead to incorrect code generation when zero-extending one register into
another. This patch adds a new output template to the define_insns to
handle such cases and produce correct asm.
gcc/ChangeLog:
* config/bpf/bpf.md (
The following patch by Steve was lingering in the PR for some time.
For an implied do loop within an array constructor we would generate an
additional, bogus substring bounds check for the index variable before it
actually became defined. The check thus depended on the previous value of
the index
Hi!
On Thu, Sep 09, 2021 at 12:19:28PM -0500, Bill Schmidt wrote:
> On 9/9/21 11:11 AM, Segher Boessenkool wrote:
> >On Wed, Sep 08, 2021 at 02:57:14PM +0800, Kewen.Lin wrote:
> >>+ /* If we have strided or elementwise loads into a vector, it's
> >"strided" is not a word: it properly is "stri
On 9/9/21 12:19 PM, Bill Schmidt wrote:
On 9/9/21 11:11 AM, Segher Boessenkool wrote:
Hi!
On Wed, Sep 08, 2021 at 02:57:14PM +0800, Kewen.Lin wrote:
+ /* If we have strided or elementwise loads into a vector, it's
+possible to be bounded by latency and execution resources for
+
On 9/9/21 11:11 AM, Segher Boessenkool wrote:
Hi!
On Wed, Sep 08, 2021 at 02:57:14PM +0800, Kewen.Lin wrote:
+ /* If we have strided or elementwise loads into a vector, it's
+possible to be bounded by latency and execution resources for
+many scalar loads. Try to account f
Hello people,
This patch add support for atomics operations in eBPF target
using the gcc built-in functions:
__atomic__fetch
__atomic_fetch_
Please if you have comments, don't hesitate to let me know.
Kinds Regards,
Guillermo
eBPF add support for basic atomic operations, the following
gcc
On Linux/x86_64,
60eec23b5eda0f350e572586eee738eab0804a74 is the first bad commit
commit 60eec23b5eda0f350e572586eee738eab0804a74
Author: liuhongt
Date: Wed Sep 8 16:19:37 2021 +0800
Optimize vec_extract for 256/512-bit vector when index exceeds the lower
128 bits.
caused
FAIL: gcc.targ
On 8/18/21 3:13 PM, Iain Sandoe wrote:
Hi,
I have found it useful when working with modules stuff to have the completed
set of command/responses available (some people working with the interfaces
for more sophisticated tools are using them). This message is a hand-shake
telling the server that
Hi!
On Wed, Sep 08, 2021 at 02:57:14PM +0800, Kewen.Lin wrote:
> >>+ /* If we have strided or elementwise loads into a vector, it's
> >>+possible to be bounded by latency and execution resources for
> >>+many scalar loads. Try to account for this by scaling the
> >>+construction
On 9/9/21 9:19 AM, Richard Biener via Gcc-patches wrote:
The following removes the unused config/dbx.h file and removes the
setting of PREFERRED_DEBUGGING_TYPE from dbxcoff.h which is
overridden by all users (djgpp/mingw/cygwin) via either including
config/i386/djgpp.h or config/i386/cygming.h
T
On Wed, Jul 21, 2021 at 12:44 AM liuhongt wrote:
>
> From: "H.J. Lu"
>
> Copied from regular XMM ABI tests. Only run AVX512FP16 ABI tests for ELF
> targets.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/x86_64/abi/avx512fp16/abi-avx512fp16-xmm.exp: New exp
> file for abi test.
>
On 9/9/2021 7:19 AM, Richard Biener via Gcc-patches wrote:
The following removes the unused config/dbx.h file and removes the
setting of PREFERRED_DEBUGGING_TYPE from dbxcoff.h which is
overridden by all users (djgpp/mingw/cygwin) via either including
config/i386/djgpp.h or config/i386/cygming
Hi, Jeff,
Sorry for the late reply.
The following is the reply from John Henning and the updated patch based on
your suggestions,
Please take a look and let us know any issue there.
Thanks.
Qing
==
Jeff Law suggested that th
On 09/09/2021 13:23, Richard Biener via Gcc-patches wrote:
On Thu, Sep 9, 2021 at 1:09 PM Richard Earnshaw wrote:
gen_lowpart_general handles forming a SUBREG of a MEM by using
adjust_address to rework and validate a new version of the MEM.
However, gen_highpart does not attempt this and s
On 9/9/21 1:19 PM, Richard Biener wrote:
The following removes the unused config/dbx.h file and removes the
setting of PREFERRED_DEBUGGING_TYPE from dbxcoff.h which is
overridden by all users (djgpp/mingw/cygwin) via either including
config/i386/djgpp.h or config/i386/cygming.h
There are still c
The following removes the unused config/dbx.h file and removes the
setting of PREFERRED_DEBUGGING_TYPE from dbxcoff.h which is
overridden by all users (djgpp/mingw/cygwin) via either including
config/i386/djgpp.h or config/i386/cygming.h
There are still circumstances where mingw and cygwin default
On Thu, 2021-09-09 at 07:45 +, Petter Tomner wrote:
> Hi,
>
> I tested it on another machine over ssh and newer gdb:s (8.3+) clobbers
> the output with color escapes so I had to disable colors
> for the gdb session in jit.exp for the regex matching to work properly:
>
> + verbose "Disable
On 21 Jul 2021, Alan Modra uttered the following:
> On Wed, Jul 07, 2021 at 08:03:45PM +0100, Nick Alcock via Gcc-patches wrote:
>> >>> PR libctf/27482
>> >>> * libtool.m4 (LT_PATH_NM): Try BSDization flags with a user-provided
>> >
>> > Changes to libtool need to be posted to the libtool project
On Thu, Sep 9, 2021 at 1:09 PM Richard Earnshaw wrote:
>
>
> gen_lowpart_general handles forming a SUBREG of a MEM by using
> adjust_address to rework and validate a new version of the MEM.
> However, gen_highpart does not attempt this and simply returns (SUBREG
> (MEM)) if the change is not 'obvi
On Thu, Sep 9, 2021 at 12:08 PM Roger Sayle wrote:
>
>
> As observed by Jakub in comment #2 of PR 98865, the expression -(a>>63)
> is optimized in GENERIC but not in GIMPLE. Investigating further it
> turns out that this is one of a few transformations performed by
> fold_negate_expr in fold-cons
The current restriction on folding memcpy to a single element of size
MOVE_MAX is excessively cautious on most machines and limits some
significant further optimizations. So relax the restriction provided
the copy size does not exceed MOVE_MAX * MOVE_RATIO and that a SET
insn exists for moving th
DImode is currently handled only for machines with vector modes
enabled, but this is unduly restrictive and is generally better done
in core registers.
gcc/ChangeLog:
PR target/102125
* config/arm/arm.md (movmisaligndi): New define_expand.
* config/arm/vec-common.md (movm
gen_lowpart_general handles forming a SUBREG of a MEM by using
adjust_address to rework and validate a new version of the MEM.
However, gen_highpart does not attempt this and simply returns (SUBREG
(MEM)) if the change is not 'obviously' safe. Improve on that by
using a similar approach so that g
Changes since version 1:
patch 1 is reworked entirely to handle SUBREG (MEM) in gen_highpart. This
brings it more in line with the way gen_lowpart_general handles this case.
patch 2 is simplified because, having reread the manual description of
movmisalign I realised that this pattern can never
On Thu, 9 Sept 2021 at 15:38, Roger Sayle wrote:
>
>
> As observed by Jakub in comment #2 of PR 98865, the expression -(a>>63)
> is optimized in GENERIC but not in GIMPLE. Investigating further it
> turns out that this is one of a few transformations performed by
> fold_negate_expr in fold-const.
On Thu, 9 Sep 2021, Richard Biener wrote:
> On Thu, 9 Sep 2021, Xionghu Luo wrote:
>
> >
> >
> > On 2021/9/2 18:37, Richard Biener wrote:
> > > On Thu, 2 Sep 2021, Xionghu Luo wrote:
> > >
> > >>
> > >>
> > >> On 2021/9/2 16:50, Richard Biener wrote:
> > >>> On Thu, 2 Sep 2021, Richard Biener
As observed by Jakub in comment #2 of PR 98865, the expression -(a>>63)
is optimized in GENERIC but not in GIMPLE. Investigating further it
turns out that this is one of a few transformations performed by
fold_negate_expr in fold-const.c that aren't yet performed by match.pd.
This patch moves/dup
On Thu, 9 Sep 2021, Xionghu Luo wrote:
>
>
> On 2021/9/2 18:37, Richard Biener wrote:
> > On Thu, 2 Sep 2021, Xionghu Luo wrote:
> >
> >>
> >>
> >> On 2021/9/2 16:50, Richard Biener wrote:
> >>> On Thu, 2 Sep 2021, Richard Biener wrote:
> >>>
> On Thu, 2 Sep 2021, Xionghu Luo wrote:
>
On Thu, Sep 9, 2021 at 3:54 PM liuhongt wrote:
>
> Hi:
> As a follow up of [1], the patch removes all scalar mode copysign related
> post_reload splitter/define_insn and expand copysign directly into below using
> paradoxical subregs.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2021-September
Hi:
As a follow up of [1], the patch removes all scalar mode copysign related
post_reload splitter/define_insn and expand copysign directly into below using
paradoxical subregs.
op3 = op1 & ~mask;
op4 = op2 & mask;
dest = op3 | op4;
It can sometimes generate better code just like avx512dq
Hi,
I tested it on another machine over ssh and newer gdb:s (8.3+) clobbers the
output with color escapes so I had to disable colors
for the gdb session in jit.exp for the regex matching to work properly:
+verbose "Disable color styling in GDB newer then 8.3 (errors on older)"
+send "set
On Thu, Jul 1, 2021 at 2:17 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> * config.gcc: Add avx512fp16vlintrin.h.
> * config/i386/avx512fp16intrin.h: (_mm512_add_ph): New intrinsic.
> (_mm512_mask_add_ph): Likewise.
> (_mm512_maskz_add_ph): Likewise.
> (_mm512_s
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