Re: [PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative.

On Tue, Jul 19, 2022 at 2:35 PM Uros Bizjak via Gcc-patches wrote: > > On Tue, Jul 19, 2022 at 8:07 AM liuhongt wrote: > > > > And split it after reload. > > > > > You will need ix86_binary_operator_ok insn constraint here with > > > corresponding expander using ix86_fixup_binary_operands_no_copy

Re: [PATCH] match.pd: Add new abs pattern [PR94290]

On Mon, Jul 18, 2022 at 7:31 PM Sam Feifer via Gcc-patches wrote: > > Just realized I had mixed up the 9 and the 2 when labelling the patch. This > patch is referring to pr94920 not pr94290. Attached is a fixed patch file. > Sorry for any confusion. Can you put the patterns somewhere related? Th

Re: [PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative.

On Tue, Jul 19, 2022 at 8:07 AM liuhongt wrote: > > And split it after reload. > > > You will need ix86_binary_operator_ok insn constraint here with > > corresponding expander using ix86_fixup_binary_operands_no_copy to > > prepare insn operands. > Split define_expand with just register_operand, a

[PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative.

And split it after reload. > You will need ix86_binary_operator_ok insn constraint here with > corresponding expander using ix86_fixup_binary_operands_no_copy to > prepare insn operands. Split define_expand with just register_operand, and allow memory/immediate in define_insn, assume combine/forwp

Re: [PATCH] xtensa: Correct the relative RTX cost that corresponds to the Move Immediate "MOVI" instruction

On Mon, Jul 18, 2022 at 5:47 AM Takayuki 'January June' Suwa wrote: > > This patch corrects the overestimation of the relative cost of > '(set (reg) (const_int N))' where N fits into the instruction itself. > > In fact, such overestimation confuses the RTL loop invariant motion pass. > As a result

RE: [PATCH] Add a heuristic for eliminate redundant load and store in inline pass.

Hi Honza, Gentle ping https://gcc.gnu.org/pipermail/gcc-patches/2022-July/597891.html Thanks, Lili. > -Original Message- > From: Gcc-patches On > Behalf Of Cui, Lili via Gcc-patches > Sent: Sunday, July 10, 2022 10:05 PM > To: Jan Hubicka > Cc: Lu, Hongjiu ; Liu, Hongtao > ; gcc-patche

[PATCH] avr: Removed errant control characters

Signed-off-by: Joel Holdsworth --- gcc/config/avr/avr-devices.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/gcc/config/avr/avr-devices.cc b/gcc/config/avr/avr-devices.cc index aa284217f50..ff6a5441b77 100644 --- a/gcc/config/avr/avr-devices.cc +++ b/gcc/config/avr/avr-devices.cc @@ -126

Re: [PATCH] c++: shortcut bad reference bindings [PR94894]

On 7/18/22 12:59, Patrick Palka wrote: In case of l/rvalue or cv-qual mismatch during reference binding, we try to give more helpful diagnostics by attempting a bad conversion that ignores the mismatch. But in doing so, we may end up instantiating an ill-formed conversion function, something tha

[PATCH] Fortran: error recovery on invalid array reference of non-array [PR103590]

Dear all, I intend to commit the attached patch as obvious to mainline within the next 24h unless someone complains. It replaces a lazy gfc_internal_error by an explicit error message and an error recovery path. As a side-effect, we now diagnose a previously missed error in testcase gfortran.dg/

[COMMITTED] tree-optimization/106280 - Check if transitives need to be registered.

Regardless of whether this is enough of an improvement for the PR, it should be done. Whenever a relation is registered with the oracle, it walks the dominator tree trying to apply any transitives it can find. FIrst, it should check whether the operands are already in any relation. If neithe

Re: [PATCH] match.pd: Add new abs pattern [PR94290]

Just realized I had mixed up the 9 and the 2 when labelling the patch. This patch is referring to pr94920 not pr94290. Attached is a fixed patch file. Sorry for any confusion. On Mon, Jul 18, 2022 at 9:07 AM Sam Feifer wrote: > Here's an updated version of the patch. > > Thanks > -Sam > > On Thu

[PATCH] c++: shortcut bad reference bindings [PR94894]

In case of l/rvalue or cv-qual mismatch during reference binding, we try to give more helpful diagnostics by attempting a bad conversion that ignores the mismatch. But in doing so, we may end up instantiating an ill-formed conversion function, something that would otherwise be avoided if we didn't

[PATCH] RISC-V: Add RTX costs for `if_then_else' expressions

Fix a performance regression from commit 391500af1932 ("Do not ignore costs of jump insns in combine."), a part of the m68k series for MODE_CC conversion (), observed in soft-fp code in libgcc used by some of the embench-iot benchmarks.

Re: [PATCH] ipa-cp: Fix assert triggering with -fno-toplevel-reorder (PR 106260)

Hi, On Mon, Jul 18 2022, Jan Hubicka wrote: >> Hi, >> >> with -fno-toplevel-reorder (and -fwhole-program), there apparently can >> be local functions without any callers. This is something that IPA-CP > > If there is possibility to trigger a local function without callers, I > think one can also

[committed] RISC-V/doc: Add index references for `mrelax' and `mriscv-attribute'

Add missing index references for the `-mrelax' and `-mriscv-attribute' invocation options. gcc/ * doc/invoke.texi (RISC-V Options): Add index references for `mrelax' and `mriscv-attribute'. --- Hi, Verified with `make info pdf' and committed as obvious. Maciej --- g

[committed] RISC-V/doc: Correct the formatting of `-mstack-protector-guard-reg='

Add missing second space around the `-mstack-protector-guard-reg=' invocation option. gcc/ * doc/invoke.texi (Option Summary): Add missing second space around `-mstack-protector-guard-reg='. --- Hi, Verified with `make info pdf' and committed as obvious. Maciej ---

[committed] RISC-V/doc: Correct the name of `-mriscv-attribute'

Correct the name of the `-mriscv-attribute' invocation option, including a typo in the negated form. gcc/ * doc/invoke.texi (Option Summary): Fix `-mno-riscv-attribute'. (RISC-V Options): Likewise, and `-mriscv-attribute'. --- Hi, Verified with `make info pdf' and commit

[PING][PATCH v2] RISC-V: Split unordered FP comparisons into individual RTL insns

On Mon, 4 Jul 2022, Maciej W. Rozycki wrote: > These instructions are only produced via an expander already, so change > the expander to emit individual RTL insns for each machine instruction > in the ultimate ultimate sequence produced rather than deferring to a > single RTL insn producing the

Re: [PATCH] match.pd: Add new abs pattern [PR94290]

Here's an updated version of the patch. Thanks -Sam On Thu, Jul 14, 2022 at 3:54 PM Andrew Pinski wrote: > On Thu, Jul 14, 2022 at 12:38 PM Sam Feifer wrote: > > > > > > > > On Thu, Jul 14, 2022 at 1:24 PM Andrew Pinski wrote: > >> > >> On Thu, Jul 14, 2022 at 7:09 AM Sam Feifer wrote: > >>

[PATCH] xtensa: Correct the relative RTX cost that corresponds to the Move Immediate "MOVI" instruction

This patch corrects the overestimation of the relative cost of '(set (reg) (const_int N))' where N fits into the instruction itself. In fact, such overestimation confuses the RTL loop invariant motion pass. As a result, it brings almost no negative impact from the speed point of view, but addtiion

[committed] arc: Add ARCHS release 310a tune variant.

Add mtune and mcpu options for ARCHS release 310a type CPU. The mtune=release31a is designed to be used as an alternative to the mcpu=hs4x_rel31 option. ARCHS4x release 31a uses DSP instructions which are implemented a bit different than mpy9. Hence, use safer mpy2 option. gcc/ * config/ar

[PATCH] Fix builtin vs non-builtin partition merge in loop distribution

When r7-6373-g40b6bff965d004 fixed a costing issue it failed to make the logic symmetric which means that we now fuse normal vs. builtin when the cost model says so but we don't fuse builtin vs. normal. The following fixes that, also allowing the cost model to decide to fuse two builtin partitions

[committed 2/2] libgcc/arc: Update udivmodsi4 and make the lib safe for rf16

From: Claudiu Zissulescu The ARC soft udivmodsi4 algorithm and as well as using umodsi3 for reduced register set configurations are wrong. libgcc/ * config/arc/lib2funcs.c (udivmodsi4): Update AND mask. * config/arc/lib1funcs.S (umodsi3): Don't use it for RF16 configurati

[committed 1/2] arc: Fix interrupt's epilogue.

The stack pointer adjustment in interrupt epilogue is happening after restoring the ZOL registers which is wrong. Fixing this. gcc/ * config/arc/arc.cc (arc_expand_epilogue): Adjust the frame pointer first when in interrupts. gcc/testsuite/ * gcc.target/arc/interrupt-13.c:

[committed] arc: Fix interrupt's epilogue.

The stack pointer adjustment in interrupt epilogue is happening after restoring the ZOL registers which is wrong. Fixing this. gcc/ * config/arc/arc.cc (arc_expand_epilogue): Adjust the frame pointer first when in interrupts. gcc/testsuite/ * gcc.target/arc/interrupt-13.c:

[PATCH] Improve common reduction vs builtin code generation in loop distribution

loop distribution currently cannot handle the situation when the last partition is a builtin but there's a common reduction in all partitions (like the final IV value). The following lifts this restriction by making the last non-builtin partition provide the definitions for the loop-closed PHI nod

Re: [PATCH] Simplify branching in algos

On Mon, 18 Jul 2022 at 11:25, François Dumont wrote: > > Hi > > I just noticed that I still had this nice enhancement in my local > branches. > > Ok to commit ? OK, thanks.

RE: [PATCH] arm: Replace arm_builtin_vectorized_function [PR106253]

> -Original Message- > From: Richard Sandiford > Sent: Wednesday, July 13, 2022 9:14 AM > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw ; Kyrylo Tkachov > > Subject: [PATCH] arm: Replace arm_builtin_vectorized_function [PR106253] > > This patch extends the fix for PR106253 to AArc

Re: [PATCH] aarch64: Replace manual swapping idiom with std::swap in aarch64.cc

Richard Ball writes: > Replace manual swapping idiom with std::swap in aarch64.cc > > gcc/config/aarch64/aarch64.cc has a few manual swapping idioms of the form: > > x = in0, in0 = in1, in1 = x; > > The preferred way is using the standard: > > std::swap (in0, in1); > > We should just fix these to

Re: [PATCH] Simplify branching in algos

Hi     I just noticed that I still had this nice enhancement in my local branches.     Ok to commit ? François On 21/11/21 21:34, François Dumont wrote: A recent thread on this mailing list made me remember that this proposal is still open. I've updated it just to add a missing std qualif

Re: [PATCH] ipa-cp: Fix assert triggering with -fno-toplevel-reorder (PR 106260)

> Hi, > > with -fno-toplevel-reorder (and -fwhole-program), there apparently can > be local functions without any callers. This is something that IPA-CP If there is possibility to trigger a local function without callers, I think one can also make two local functions calling each other but with

Re: Re: [PATCH] libstdc++: Make __from_chars_alnum_to_val conversion explicit

(in reply to https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598412.html, adding libstdc++ to CC, with the same patch attached again) To clarify, this is not a fix for a user-facing issue of gcc or a fix for UB. It is just a minor UX improvement for developers that use the clang integer saniti

Re: [PATCH v3, rs6000] Disable TImode from Bool expanders [PR100694, PR93123]

Hi Segher, Thanks for your comments. On 13/7/2022 上午 1:26, Segher Boessenkool wrote: >> --- a/gcc/config/rs6000/rs6000.md >> +++ b/gcc/config/rs6000/rs6000.md >> @@ -7078,27 +7078,38 @@ (define_expand "subti3" >> }) >>  >> ;; 128-bit logical operations expanders >> +;; Fail TImode in all 128

Re: [Ada] Fix typos in comments

OK, thanks.