On 2022-10-21 11:44, Eric Botcazou via Libstdc++ wrote:
How does this compare with Eric B's proposal at
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-06/msg01840.html ?
My proposal was to reimplement (and extend) the native thread model
(win32)
instead of adding a new one, the advantage being
On Sun, 23 Oct 2022, ibuc...@gdcproject.org wrote:
> > On 17/10/2022 20:08 CEST Iain Buclaw wrote:
> >
> >
> > Hi,
> >
> > This splits up the targetdm sources so that each file only handles one
> > target platform.
> >
> > Having all logic kept in the headers means that they could become out
> From: Gcc-patches
> On Behalf Of Hongtao Liu via Gcc-patches
> Sent: Monday, October 17, 2022 1:47 PM
> To: Jiang, Haochen
> Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
>
> On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
> wr
PING
On Mon, Oct 17, 2022 at 8:21 AM Aldy Hernandez wrote:
>
> On Thu, Oct 13, 2022 at 7:57 PM Jakub Jelinek wrote:
> >
> > On Thu, Oct 13, 2022 at 02:36:49PM +0200, Aldy Hernandez wrote:
> > > +// Like real_arithmetic, but round the result to INF if the operation
> > > +// produced inexact resu
在 2022/10/21 20:34, i.nix...@autistici.org 写道:
got it...
anyway it seems logical to me the way I proposed :)
Below is a message forwarded from mingw-w64-public, elaborating the necessity
of a new thread model.
As there are objections from other mingw-w64 developers, I am putting those patc
Hi,
This patch implements V8HI byte reverse on Power8 by vector rotation.
It should be effecient than orignial vector permute. The patch comes from
Xionghu's comments in PR. I just added a test case for it.
Bootstrapped and tested on ppc64 Linux BE and LE with no regressions.
Is this okay for
Merged two changes into one patch, and committed to master :)
On Mon, Oct 24, 2022 at 10:28 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Adjust using
> force_reg.
>
> ---
> gcc/config/riscv/riscv.cc | 4 +---
> 1 file changed,
Hi Hongtao,
This patch introduces function finish_cost and
determine_suggested_unroll_factor for x86 backend, to make it be
able to suggest the unroll factor for a given loop being vectorized.
Referring to aarch64, RS6000 backends and basing on the analysis on
SPEC2017 performance evaluation resu
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.
---
gcc/config/riscv/riscv.cc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 98374a922d1..1fd34
Committed, thanks!
On Mon, Oct 24, 2022 at 10:21 AM wrote:
>
> From: Ju-Zhe Zhong
>
> Move away from the pre-C++11 compatibility macro CONSTEXPR.
> This patch is inspired by aarch64:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603974.html.
>
> gcc/ChangeLog:
>
> * config/ris
Address comments. Fix it soon.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2022-10-24 10:14
To: juzhe.zhong
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
On Sun, Oct 23, 2022 at 7:04 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
>
Committed, thanks :)
On Mon, Oct 24, 2022 at 10:06 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF
> vector modes.
>
> ---
> gcc/config/riscv/riscv-vector-switch.def | 4
> 1 file changed, 4 deletions(-)
>
From: Ju-Zhe Zhong
Move away from the pre-C++11 compatibility macro CONSTEXPR.
This patch is inspired by aarch64:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603974.html.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Replace CONSTEXPR
with constexpr th
Committed, thanks for the fix!
On Mon, Oct 24, 2022 at 9:39 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h (enum reg_class): Fix ALL_REGS.
>
> ---
> gcc/config/riscv/riscv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/conf
On Sun, Oct 23, 2022 at 7:04 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
> (const_poly_int)).
>
> ---
> gcc/config/riscv/riscv.cc | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/gcc/
From: Ju-Zhe Zhong
---
gcc/config.gcc| 2 +-
gcc/config/riscv/constraints.md | 22 +
gcc/config/riscv/predicates.md| 23 ++
gcc/config/riscv/riscv-protos.h | 14 +
gcc/config/riscv/riscv-v.cc | 180
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF
vector modes.
---
gcc/config/riscv/riscv-vector-switch.def | 4
1 file changed, 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-switch.def
b/gcc/config/riscv/riscv-ve
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
(const_poly_int)).
---
gcc/config/riscv/riscv.cc | 14 ++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a390
I made a mistake in this patch. I mixed 2 commits into a single patch.
Sorry about that. Please ignore this patch. Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2022-10-24 09:53
To: gcc-patches
CC: kito.cheng; palmer; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Support (set (mem) (const_poly_
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove TI/TF.
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
(const_poly_int)).
---
gcc/config/riscv/riscv-vector-switch.def | 4
gcc/config/riscv/riscv.cc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.h (enum reg_class): Fix ALL_REGS.
---
gcc/config/riscv/riscv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index acae68ebb2d..37363e975e1 100644
--- a/gcc/
Both current lld and the next version of ld have an option -pdb, which
creates a PDB file which Microsoft's debuggers can use. This patch adds
a -gcodeview option, which passes this to the linker.
I do intend to expand this so it also creates the .debug$S and .debug$T
sections which would make thi
The Plan 9 compilers defer duplicate declaration checks until field
resolution time. Further, there is a priority order of resolution such
that field lookups first match the name, then typedef'd names before
recursing into substructures.
This enables large portions of the Plan 9 userspace and ker
[Jakub and other FP experts, would this be OK, or am I missing
something?]
Vax does not seem to have !flag_finite_math_only, but float_type_node
does not HONOR_NANS. The check in frange::verify_range dependend on
flag_finite_math_only, which is technically not correct since
frange::set_varying()
[AMD Official Use Only - General]
Hi Richi and Jakub
> -Original Message-
> From: Jakub Jelinek
> Sent: Saturday, October 22, 2022 10:41 PM
> To: Richard Biener
> Cc: Kumar, Venkataramanan ; Joshi,
> Tejas Sanjay ; gcc-patches@gcc.gnu.org;
> honza.hubi...@gmail.com
> Subject: Re: [PATCH
On Friday, 21 October 2022 23:02:02 CEST Joseph Myers wrote:
> I have no objections to the C changes.
Great! Thanks for the review. I don't have push rights currently, so I
must ask that someone else pushes this patch for me.
Have a great day!
--
Arsen Arsenović
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> On 17/10/2022 20:08 CEST Iain Buclaw wrote:
>
>
> Hi,
>
> This splits up the targetdm sources so that each file only handles one
> target platform.
>
> Having all logic kept in the headers means that they could become out of
> sync when a new target is added (loongarch*-*-linux*) or acciden
When linking with -static-pie, we need to use rcrt0.o (and grcrt0.o for
-pg). Also, set static:crt0.o before pie:Scrt1.o, otherwise -static -pie
fails to link with Scrt1.o due to missing _DYNAMIC symbol.
Also, -static-pie needs crtbeginS.o (otherwise it contains a relocation
in read-only .text).
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