Re: PING^5 [PATCH] testsuite: Verify that module-mapper is available

On Thu, Nov 17, 2022 at 6:09 PM Torbjorn SVENSSON via Gcc-patches wrote: > > Hi, > > Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604895.html > > Ok for trunk? OK. > Kind regards, > Torbjörn > > On 2022-11-02 19:13, Torbjorn SVENSSON wrote: > > Hi, > > > > Ping, https://gcc.gnu.

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, Nov 17, 2022 at 8:38 PM Jakub Jelinek via Gcc-patches wrote: > > On Thu, Nov 17, 2022 at 06:59:45PM +, Joseph Myers wrote: > > On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > > > > > So... is the optimization wrong? Are we not allowed to substitute > > > that NAN if we kn

Re: [PATCH] libcpp: Add missing config for --enable-valgrind-annotations [PR107691]

On Thu, Nov 17, 2022 at 10:04 PM Bernhard Reutner-Fischer via Gcc-patches wrote: > > --- > ceb17928e5d1d5 copied (parts of) the valgrind annotation checks from gcc > to libcpp. The above copies the missing pieces to libcpp to diagnose > when libcpp is configured with --enable-valgrind-annotations

Re: [PATCH 2/2] Fix PR middle-end/107705: ICE after reclaration error

On Fri, Nov 18, 2022 at 4:26 AM apinski--- via Gcc-patches wrote: > > From: Andrew Pinski > > The problem here is after we created a call expression > in the C front-end, we replace the decl type with > an error mark node. We then end up calling > aggregate_value_p with the call expression > with

Re: [PATCH 1/2] Fix PRs 106764, 106765, and 107307, all ICE after invalid re-declaration

On Fri, Nov 18, 2022 at 4:26 AM apinski--- via Gcc-patches wrote: > > From: Andrew Pinski > > The problem here is the gimplifier returns GS_ERROR but > in some cases we don't check that soon enough and try > to do other work which could crash. > So the fix in these two cases is to return GS_ERROR

Re: [PATCH] optimize the testcase for architectures that use ".srodata"

On Fri, Nov 18, 2022 at 6:49 AM Yixuan Chen wrote: OK. > 2022-11-18 Yixuan Chen > > * gcc.dg/pr25521.c: optimize the testcast for architectures that use > ".srodata" > > testsuite/gcc.dg/pr25521.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/testsuite/

[PATCH][committed] aarch64: Fix up LDAPR codegen

Hi all, Upon some further inspection I realised I had misunderstood some intricacies of the extending loads of the RCPC feature. This patch fixes up the recent GCC support accordingly. In particular: * The sign-extending forms are a form of LDAPURS* and are actually part of FEAT_RCPC2 that is en

Re: [PATCH] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

On Fri, Nov 18, 2022 at 6:09 AM Palmer Dabbelt wrote: > On Thu, 17 Nov 2022 18:12:23 PST (-0800), christoph.muell...@vrull.eu > wrote: > > From: Christoph Müllner > > > > This patch adds support for the two AIA ISA extensions Ssaia and Smaia. > > They are not relelvant for the compiler, but the

[PATCH] c++, v5: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 07:28:56PM -0500, Jason Merrill wrote: > On 11/17/22 15:42, Jakub Jelinek wrote: > > On Thu, Nov 17, 2022 at 07:42:40PM +0100, Jakub Jelinek via Gcc-patches > > wrote: > > > I thought for older C++ this is to catch > > > void > > > foo () > > > { > > >constexpr int a =

Re: [PATCH] RISC-V: branch-(not)equals-zero compares against $zero

On Fri, 18 Nov 2022 at 05:53, Palmer Dabbelt wrote: > > On Thu, 17 Nov 2022 14:44:31 PST (-0800), jeffreya...@gmail.com wrote: > > > > On 11/8/22 12:55, Philipp Tomsich wrote: > >> If we are testing a register or a paradoxical subreg (i.e. anything that > >> is not > >> a partial subreg) for equa

Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector

Hongtao Liu writes: > On Thu, Nov 17, 2022 at 9:59 PM Richard Sandiford > wrote: >> >> Hongtao Liu writes: >> > On Thu, Nov 17, 2022 at 5:39 PM Richard Sandiford >> > wrote: >> >> >> >> Hongtao Liu writes: >> >> > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford >> >> > wrote: >> >> >> >> >>

Re: [PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

Richard Sandiford via Gcc-patches writes: > Tamar Christina writes: >> Hi All, >> >> While writing a patch series I started getting incorrect codegen out from >> VEC_PERM on partial struct types. >> >> It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS >> implementation

RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

Hi, > -Original Message- > From: Ramana Radhakrishnan > Sent: Thursday, November 17, 2022 8:27 PM > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding > instruction "0xb5". > >

RE: [PATCH 01/35] arm: improve vcreateq* tests

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 01/35] arm: improve vcreateq* tests > > gcc/testsuite/ChangeLog: > > * gcc.target/a

Re: [PATCH] 3/19 modula2 front end: gm2 driver files.

On Mon, Oct 10, 2022 at 5:33 PM Gaius Mulley via Gcc-patches wrote: > > > > This patchset contains the c++, h and option related files necessary > to build the driver program gm2. The patch also consists of the > autoconf/configure related build infastructure sources found in > gcc/m2. The revie

Re: [PATCH] 8/19 modula2 front end: libgm2 contents

On Mon, Oct 10, 2022 at 5:35 PM Gaius Mulley via Gcc-patches wrote: > > > > This patch set consists of the libgm2 makefile, autoconf sources > necessary to build the libm2pim, libm2iso, libm2min, libm2cor > and libm2log. This looks OK. I suppose it was also tested building a cross-compiler? Can

Re: PING^5 [PATCH] testsuite: Verify that module-mapper is available

On 2022-11-18 09:14, Richard Biener wrote: On Thu, Nov 17, 2022 at 6:09 PM Torbjorn SVENSSON via Gcc-patches wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604895.html Ok for trunk? OK. Pushed. Kind regards, Torbjörn On 2022-11-02 19:13, Torbjorn SVENSSO

Re: [PATCH] [range-ops] Implement sqrt.

On 11/18/22 09:39, Richard Biener wrote: On Thu, Nov 17, 2022 at 8:38 PM Jakub Jelinek via Gcc-patches wrote: On Thu, Nov 17, 2022 at 06:59:45PM +, Joseph Myers wrote: On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: So... is the optimization wrong? Are we not allowed to s

Re: [PATCH] [range-ops] Implement sqrt.

On Fri, Nov 18, 2022 at 11:37:42AM +0100, Aldy Hernandez wrote: > > Practically strictly > > preserving IEEE exceptions is only important for a very small audience, and > > for that even INEXACT will matter (but we still have -ftrapping-math > > by default). > > For that audience likely all constan

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On Thu, 17 Nov 2022 18:52:36 -0500 Jason Merrill wrote: > On 11/17/22 14:02, Bernhard Reutner-Fischer wrote: > > On Thu, 17 Nov 2022 09:53:32 -0500 > > Jason Merrill wrote: > >> Instead, you want to copy the location for instantiations, i.e. check > >> DECL_TEMPLATE_INSTANTIATION instead of !DE

[PATCH v2 0/2] Use Zbs with xori/ori/andi and polarity-reversed twobit-tests

We had a few patches on the list that shared predicates (for extending the reach of xori and ori -- and for the branches on two polarity-reversed bits) and thus depended on each other. These all had approval with requested changes, so these are now collected together for v2. Note that this adds

[PATCH v2 1/2] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori

Sequences of the form "a | C" and "a ^ C" with C being the positive half of a signed immediate's range with one extra bit set in addition are mapped to ori/xori and one bseti/binvi to avoid using a temporary (and a multi-insn sequence to load C into that temporary). Something similar holds for "a

[PATCH v2 2/2] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." that can be expressed as bexti + bexti + andn. gcc/ChangeLog: * config/riscv/bitmanip.md (*branch_mask_twobits_equals_singlebit): Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set

Re: [PATCH] [range-ops] Implement sqrt.

On 11/18/22 11:44, Jakub Jelinek wrote: On Fri, Nov 18, 2022 at 11:37:42AM +0100, Aldy Hernandez wrote: Practically strictly preserving IEEE exceptions is only important for a very small audience, and for that even INEXACT will matter (but we still have -ftrapping-math by default). For that a

Re: [PATCH] Fortran: reject NULL actual argument without explicit interface [PR107576]

Le 17/11/2022 à 21:48, Harald Anlauf via Fortran a écrit : Dear all, one cannot pass a NULL actual argument to a procedure without an explicit interface. This is detected and reported by NAG and Intel. (Cray accepts this silently, and some other brands ICE.) The testcase by Gerhard even tricke

Re: [PATCH] [range-ops] Implement sqrt.

I wonder if instead of disabling ranger altogether, we could disable code changes (constant propagation, jump threading and simplify_using_ranges)? Or does that sound like too much hassle? It seems that some passes (instruction selection?) could benefit from global ranges being available even if n

Re: [PATCH] [range-ops] Implement sqrt.

> Am 18.11.2022 um 11:44 schrieb Jakub Jelinek : > > On Fri, Nov 18, 2022 at 11:37:42AM +0100, Aldy Hernandez wrote: >>> Practically strictly >>> preserving IEEE exceptions is only important for a very small audience, and >>> for that even INEXACT will matter (but we still have -ftrapping-math

Re: [PATCHv2, rs6000] Enable have_cbranchcc4 on rs6000

On Fri, Nov 18, 2022 at 02:35:30PM +0800, HAO CHEN GUI wrote: > 在 2022/11/17 21:24, David Edelsohn 写道: > > Why are you using zero_constant predicate instead of matching (const_int 0) > > for operand 2? > The "const_int 0" is an operand other than a predicate. We need a predicate > here. Said dif

Re: [PATCHv2, rs6000] Enable have_cbranchcc4 on rs6000

On Fri, Nov 18, 2022 at 7:20 AM Segher Boessenkool < seg...@kernel.crashing.org> wrote: > On Fri, Nov 18, 2022 at 02:35:30PM +0800, HAO CHEN GUI wrote: > > 在 2022/11/17 21:24, David Edelsohn 写道: > > > Why are you using zero_constant predicate instead of matching > (const_int 0) for operand 2? > >

Re: [PATCH] 15/19 modula2 front end: cc1gm2 additional non modula2 source files

On Mon, Oct 10, 2022 at 5:44 PM Gaius Mulley via Gcc-patches wrote: > > > > This patch set contains the .h, .cc and .flex files found in > gcc/m2. The files are tightly coupled with the gimple interface > (see 04-gimple-interface) and built using the rules found in > (01-03-make). > > > --8<-

Re: [PATCH v2] match.pd: rewrite select to branchless expression

On Fri, Nov 11, 2022 at 3:28 AM Michael Collison wrote: > > This patches transforms ((x & 0x1) == 0) ? y : z y -into > (-(typeof(y))(x & 0x1) & z) y, where op is a '^' or a '|'. It also > transforms (cond (and (x , 0x1) != 0), (z op y), y ) into (-(and (x , > 0x1)) & z ) op y. > > Matching this

Re: [PATCH Rust front-end v3 38/46] gccrs: Add HIR to GCC GENERIC lowering entry point

On Tue, Nov 15, 2022 at 2:46 PM Arthur Cohen wrote: > > > > On 11/9/22 14:53, Richard Biener wrote: > > On Wed, Oct 26, 2022 at 10:37 AM wrote: > >> > >> From: Philip Herron > >> > >> This patch contains the entry point and utilities used for the lowering > >> of HIR nodes to `tree`s. It also co

Re: [PATCH 2/2] Add a new warning option -Wstrict-flex-arrays.

On Tue, 8 Nov 2022, Qing Zhao wrote: > '-Wstrict-flex-arrays' > Warn about inproper usages of flexible array members according to > the LEVEL of the 'strict_flex_array (LEVEL)' attribute attached to > the trailing array field of a structure if it's available, > otherwise accord

Re: [PATCH] Add a new target hook: TARGET_START_CALL_ARGS

On Fri, Nov 11, 2022 at 5:29 PM Richard Sandiford via Gcc-patches wrote: > > We have the following two hooks into the call expansion code: > > - TARGET_CALL_ARGS is called for each argument before arguments > are moved into hard registers. > > - TARGET_END_CALL_ARGS is called after the end of th

Re: [PATCH 2/2] aarch64: Add support for widening LDAPR instructions

Sorry for the late reply on this. I was wondering though why the check made sense. The way I see it, SI -> SI mode is either wrong or useless. So why not: if it is wrong, error (gcc_assert?) so we know it was generated wrongly somehow and fix it; if it is useless, still use this pattern as we av

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

On 11/17/22 16:56, Palmer Dabbelt wrote: On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: On 11/12/22 14:29, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1;    

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

On Fri, 18 Nov 2022 at 15:34, Jeff Law wrote: > > > On 11/17/22 16:56, Palmer Dabbelt wrote: > > On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: > >> > >> On 11/12/22 14:29, Philipp Tomsich wrote: > >>> Users might use explicit arithmetic operations to create a mask and >

Re: [PATCH] rs6000: Adjust loop_unroll_adjust to match middle-end change [PR 107692]

[ Please cc: me and Ke Wen on rs6000 patches ] On Thu, Nov 17, 2022 at 07:54:29AM +0800, Hongyu Wang wrote: > r13-3950-g071e428c24ee8c enables O2 small loop unrolling, but it breaks > -fno-unroll-loops for rs6000 with loop_unroll_adjust hook. Adjust the > option handling and target hook accordingl

RE: [PATCH][committed] aarch64: Fix up LDAPR codegen

> -Original Message- > From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo > Tkachov via Gcc-patches > Sent: Friday, November 18, 2022 9:06 AM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH][committed] aarch64: Fix up LDAPR codegen > > Hi all, > > Upon so

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Fri, Nov 18, 2022 at 08:48:32AM +0100, Jakub Jelinek wrote: > On Thu, Nov 17, 2022 at 07:15:05PM -0500, Marek Polacek wrote: > > > --- gcc/cp/decl.cc.jj 2022-11-16 14:44:43.692339668 +0100 > > > +++ gcc/cp/decl.cc2022-11-17 20:53:44.102011594 +0100 > > > @@ -5600,6 +5600,57 @@ grokty

Re: [PATCH 1/2]middle-end: Support early break/return auto-vectorization.

On Wed, 2 Nov 2022, Tamar Christina wrote: > Hi All, > > This patch adds initial support for early break vectorization in GCC. > The support is added for any target that implements a vector cbranch optab. I'm looking at this now, first some high-level questions. Why do we need a new cbranch opt

Re: [PATCH 1/2] rs6000: Emit vector fp comparison directly in rs6000_emit_vector_compare

Hi! On Thu, Nov 17, 2022 at 02:59:00PM +0800, Kewen.Lin wrote: > on 2022/11/17 02:44, Segher Boessenkool wrote: > > On Wed, Nov 16, 2022 at 02:48:25PM +0800, Kewen.Lin wrote: > >>* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Remove > >>float only comparison operators. > >

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Fri, Nov 18, 2022 at 10:03:18AM -0500, Marek Polacek wrote: > > the lambda operator() when still a template as constexpr and then > > cp_finish_decl -> diagnose_static_in_constexpr pedwarns on it. > > For the above perhaps we could figure out there is a static int k; in the > > operator() and do

Re: [PATCH] Allow prologues and epilogues to be inserted later

Jeff Law via Gcc-patches writes: > On 11/11/22 09:21, Richard Sandiford via Gcc-patches wrote: >> Arm's SME adds a new processor mode called streaming mode. >> This mode enables some new (matrix-oriented) instructions and >> disables several existing groups of instructions, such as most >> Advance

Re: [PATCH 2/2] Add a new warning option -Wstrict-flex-arrays.

Hi, Richard, Honestly, it’s very hard for me to decide what’s the best way to handle the interaction between -fstrict-flex-array=M and -Warray-bounds=N. Ideally, -fstrict-flex-array=M should completely control the behavior of -Warray-bounds. If possible, I prefer this solution. However, -Wa

Re: [PATCH 2/2] rs6000: Refine integer comparison handlings in rs6000_emit_vector_compare

Hi! On Thu, Nov 17, 2022 at 03:52:26PM +0800, Kewen.Lin wrote: > on 2022/11/17 02:58, Segher Boessenkool wrote: > > On Wed, Nov 16, 2022 at 02:51:04PM +0800, Kewen.Lin wrote: > >>/* In vector.md, we support all kinds of vector float point > >> comparison operators in a comparison rtl pat

Re: [PATCH] optimize the testcase for architectures that use ".srodata"

On 11/17/22 22:49, Yixuan Chen wrote: Subject: [PATCH] optimize the testcase for architectures that use ".srodata" From: Yixuan Chen Date: 11/17/22, 22:49 To: gcc-patches@gcc.gnu.org CC: kito.ch...@gmail.com, and...@sifive.com, oriachi...@gmail.com, jia...@iscas.ac.cn, Yixuan Chen 2022-1

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On 11/18/22 05:49, Bernhard Reutner-Fischer wrote: On Thu, 17 Nov 2022 18:52:36 -0500 Jason Merrill wrote: On 11/17/22 14:02, Bernhard Reutner-Fischer wrote: On Thu, 17 Nov 2022 09:53:32 -0500 Jason Merrill wrote: Instead, you want to copy the location for instantiations, i.e. check DECL_

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On 11/18/22 10:03, Marek Polacek wrote: On Fri, Nov 18, 2022 at 08:48:32AM +0100, Jakub Jelinek wrote: On Thu, Nov 17, 2022 at 07:15:05PM -0500, Marek Polacek wrote: --- gcc/cp/decl.cc.jj 2022-11-16 14:44:43.692339668 +0100 +++ gcc/cp/decl.cc 2022-11-17 20:53:44.102011594 +0100 @@ -5600,

Re: [PATCH 2/2] Add a new warning option -Wstrict-flex-arrays.

On Fri, Nov 18, 2022 at 03:19:07PM +, Qing Zhao wrote: > Hi, Richard, > > Honestly, it’s very hard for me to decide what’s the best way to handle the > interaction > between -fstrict-flex-array=M and -Warray-bounds=N. > > Ideally, -fstrict-flex-array=M should completely control the behavi

RE: [PATCH 02/35] arm: fix 'vmsr' spacing and register capitalization

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 02/35] arm: fix 'vmsr' spacing and register capitalization > > gcc/ChangeLog: > > *

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Fri, Nov 18, 2022 at 11:24:45AM -0500, Jason Merrill wrote: > > Right, that's the C++17 implicit constexpr for lambdas, finish_function: > > > >/* Lambda closure members are implicitly constexpr if possible. */ > >if (cxx_dialect >= cxx17 > >&& LAMBDA_TYPE_P (CP_DECL_CONTEXT (f

RE: [PATCH 03/35] arm: improve tests and fix vddupq*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 03/35] arm: improve tests and fix vddupq* > > gcc/ChangeLog: > > * config/arm/mve.m

RE: [PATCH 05/35] arm: improve vidupq* tests

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 05/35] arm: improve vidupq* tests > > gcc/testsuite/ChangeLog: > > * gcc.target/arm

RE: [PATCH 04/35] arm: improve tests and fix vdwdupq*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 04/35] arm: improve tests and fix vdwdupq* > > gcc/ChangeLog: > > * config/arm/mve.

RE: [PATCH 06/35] arm: improve tests and fix vdupq*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 06/35] arm: improve tests and fix vdupq* > > gcc/ChangeLog: > > * config/arm/mve.md

RE: [PATCH 08/35] arm: improve tests for vmin*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 08/35] arm: improve tests for vmin* > > gcc/testsuite/ChangeLog: > > * gcc.target/a

RE: [PATCH 09/35] arm: improve tests for vmax*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 09/35] arm: improve tests for vmax* > > gcc/testsuite/ChangeLog: > > * gcc.target/a

Re: [PATCH] Allow prologues and epilogues to be inserted later

On 11/18/22 08:18, Richard Sandiford wrote: Yeah, good point. How does the version below look? Tested as before. I guess it's a philosophical question what distinguishes "late compilation" from everything else, but I think it makes sense for it to mean "no code motion" (among other things).

RE: [PATCH 11/35] arm: improve tests for vabdq*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 11/35] arm: improve tests for vabdq* > > gcc/testsuite/ChangeLog: > > * gcc.target/

RE: [PATCH 12/35] arm: improve tests and fix vabsq*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 12/35] arm: improve tests and fix vabsq* > > gcc/ChangeLog: > > * config/arm/mve.md

RE: [PATCH 10/35] arm: improve tests for vabavq*

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 10/35] arm: improve tests for vabavq* > > gcc/testsuite/ChangeLog: > > * gcc.target

RE: [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Stam Markianos-Wright wri...@arm.com> > Subject: [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n > intrinsic >

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On 11/18/22 11:34, Jakub Jelinek wrote: On Fri, Nov 18, 2022 at 11:24:45AM -0500, Jason Merrill wrote: Right, that's the C++17 implicit constexpr for lambdas, finish_function: /* Lambda closure members are implicitly constexpr if possible. */ if (cxx_dialect >= cxx17 && LAMBDA_

RE: [PATCH 15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515]

> -Original Message- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Stam Markianos-Wright wri...@arm.com> > Subject: [PATCH 15/35] arm: Explicitly specify other float types for _Generic > over

Re: [PATCH] RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate

On Thu, 17 Nov 2022 22:59:08 PST (-0800), Kito Cheng wrote: Wait, what's Xgnuzihintpausestate??? I just made it up, it's defined right next to the name like those profile extensions are. I figured that's the most RISC-V way to define something like this, but we could just drop it and run wit

[Patch] gcn: Add __builtin_gcn_{get_stack_limit,first_call_this_thread_p}

This patch adds two builtins (getting end-of-stack pointer and a Boolean answer whether it was the first call to the builtin on this thread). The idea is to replace some hard-coded values in newlib, permitting to move later to a manually allocated stack on the compiler side without the need to mo

Re: [Patch] libgomp/gcn: Prepare for reverse-offload callback handling

Attached is the updated/rediffed version, which now uses the builtin instead of the 'asm("s8"). The code in principle works; that is: If no private stack variables are copied, it works. Or in other words: reverse-offload target regions that don't use firstprivate or mapping work, the rest would

Re: [Patch] gcn: Add __builtin_gcn_{get_stack_limit,first_call_this_thread_p}

On 18/11/2022 17:20, Tobias Burnus wrote: This patch adds two builtins (getting end-of-stack pointer and a Boolean answer whether it was the first call to the builtin on this thread). The idea is to replace some hard-coded values in newlib, permitting to move later to a manually allocated stac

Re: [Patch] libgomp/gcn: Prepare for reverse-offload callback handling

On 18/11/2022 17:41, Tobias Burnus wrote: Attached is the updated/rediffed version, which now uses the builtin instead of the 'asm("s8"). The code in principle works; that is: If no private stack variables are copied, it works. Or in other words: reverse-offload target regions that don't use

[PATCH] constexprify some tree variables

From: Andrew Pinski Since we use C++11 by default now, we can use constexpr for some const decls in tree-core.h. This patch does that and it allows for better optimizations of GCC code with checking enabled and without LTO. For an example generic-match.cc compiling is speed up due to the less n

Re: [PATCH RFA] libstdc++: add experimental Contracts support

On 03/11/22 15:57 -0400, Jason Merrill wrote: Tested x86_64-pc-linux-gnu. OK for trunk? -- >8 -- This patch adds the library support for the experimental C++ Contracts implementation. This now consists only of a default definition of the violation handler, which users can override through def

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On Fri, 18 Nov 2022 11:06:29 -0500 Jason Merrill wrote: > Ah, so the problem is deferred parsing of methods, rather than > templates. Building the DECL_RESULT sooner does seem like the right > approach to handling that, whether that's in grokfndecl or grokmethod. > >> I'd like to get the temp

[PATCH] gomp: Various fixes for SVE types [PR101018]

[I posted this late in stage 4 as an RFC, but it wasn't suitable for GCC 12 at that point. I kind-of dropped the ball after that, sorry.] Various parts of the omp code checked whether the size of a decl was an INTEGER_CST in order to determine whether the decl was variable-sized or not. If it wa

Re: [PATCH v2 0/2] Use Zbs with xori/ori/andi and polarity-reversed twobit-tests

On 11/18/22 04:09, Philipp Tomsich wrote: We had a few patches on the list that shared predicates (for extending the reach of xori and ori -- and for the branches on two polarity-reversed bits) and thus depended on each other. These all had approval with requested changes, so these are now col

Re: [PATCH] RISC-V: allow bseti on SImode without sign-extension

On 11/8/22 13:03, Philipp Tomsich wrote: As long as the SImode operand is not a partial subreg, we can use a bseti without postprocessing to or in a bit, as the middle end is smart enough to stay away from the signbit. gcc/ChangeLog: * config/riscv/bitmanip.md (*bsetidisi): New patter

Re: [PATCH] RISC-V: Optimize branches testing a bit-range or a shifted immediate

On 11/8/22 13:46, Philipp Tomsich wrote: gcc/ChangeLog: * config/riscv/predicates.md (shifted_const_arith_operand): (uimm_extra_bit_operand): * config/riscv/riscv.md (*branch_shiftedarith_equals_zero): (*branch_shiftedmask_equals_zero): gcc/testsuite/ChangeLog:

Re: [PATCH] RISC-V: split to allow formation of sh[123]add before divw

On 11/8/22 12:56, Philipp Tomsich wrote: When using strength-reduction, we will reduce a multiplication to a sequence of shifts and adds. If this is performed with 32-bit types and followed by a division, the lack of w-form sh[123]add will make combination impossible and lead to a slli + addw

Re: [PATCH v2] genmultilib: Add sanity check

On 11/3/22 03:52, Christophe Lyon via Gcc-patches wrote: When a list of dirnames is provided to genmultilib, its length is expected to match the number of options. If this is not the case, the build fails later for reasons not obviously related to this mistake. This patch adds a sanity check t

Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

On 11/8/22 12:57, Philipp Tomsich wrote: gcc/ChangeLog: * config/riscv/bitmanip.md: Handle corner-cases for combine when chaining slli(.uw)? + addw gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shNadd-04.c: New test. OK. Something to consider.  We're gaining a lo

Re: [PATCH] RISC-V: allow bseti on SImode without sign-extension

Applied to master. Thanks! Philipp. On Fri, 18 Nov 2022 at 20:26, Jeff Law wrote: > > On 11/8/22 13:03, Philipp Tomsich wrote: > > As long as the SImode operand is not a partial subreg, we can use a > > bseti without postprocessing to or in a bit, as the middle end is > > smart enough to stay aw

Re: [PATCH] RISC-V: Optimize branches testing a bit-range or a shifted immediate

Applied to master. Thanks! Philipp. On Fri, 18 Nov 2022 at 20:30, Jeff Law wrote: > > On 11/8/22 13:46, Philipp Tomsich wrote: > > gcc/ChangeLog: > > > > * config/riscv/predicates.md (shifted_const_arith_operand): > > (uimm_extra_bit_operand): > > * config/riscv/riscv.md > (*br

Re: [PATCH] RISC-V: split to allow formation of sh[123]add before divw

Applied to master. Thanks! --Philipp. On Fri, 18 Nov 2022 at 20:37, Jeff Law wrote: > > On 11/8/22 12:56, Philipp Tomsich wrote: > > When using strength-reduction, we will reduce a multiplication to a > > sequence of shifts and adds. If this is performed with 32-bit types > > and followed by a

Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

Applied to master. Thanks. --Philipp. On Fri, 18 Nov 2022 at 20:52, Jeff Law wrote: > > On 11/8/22 12:57, Philipp Tomsich wrote: > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md: Handle corner-cases for combine > > when chaining slli(.uw)? + addw > > > > gcc/testsuite/ChangeLog

Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

On Fri, 18 Nov 2022 at 20:52, Jeff Law wrote: > Something to consider. We're gaining a lot of > > (subreg:SI (reg:DI) 0) kinds of operands. > > > Would it make sense to make an operand predicate that accepted > > (reg:SI) or (subreg:SI (reg:DI) 0)? > > > It will reduce my compaints about subregs

Re: [PATCH v2 0/2] Use Zbs with xori/ori/andi and polarity-reversed twobit-tests

(Both) applied to master. Thanks! --Philipp. On Fri, 18 Nov 2022 at 20:13, Jeff Law wrote: > > On 11/18/22 04:09, Philipp Tomsich wrote: > > We had a few patches on the list that shared predicates (for extending > > the reach of xori and ori -- and for the branches on two > > polarity-reversed b

Re: [PATCH] constexprify some tree variables

On 11/18/22 11:05, apinski--- via Gcc-patches wrote: From: Andrew Pinski Since we use C++11 by default now, we can use constexpr for some const decls in tree-core.h. This patch does that and it allows for better optimizations of GCC code with checking enabled and without LTO. For an example

Re: [PATCH] RISC-V: Fix RVV testcases.

On 11/5/22 18:13, Kito Cheng via Gcc-patches wrote: Alternative fix for those testcase has posted: https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605126.html Did this ever get addressed, in either form? jeff

Re: [PATCH v2] RISC-V: No extensions for SImode min/max against safe constant

On 11/8/22 17:06, Philipp Tomsich wrote: Optimize the common case of a SImode min/max against a constant that is safe both for sign- and zero-extension. E.g., consider the case int f(unsigned int* a) { const int C = 1000; return *a * 3 > C ? C : *a * 3; } where the constant C

Re: [PATCH v2] libcpp: Avoid remapping filenames within directives

On 11/2/22 04:47, Richard Purdie via Gcc-patches wrote: Code such as: #include __FILE__ can interact poorly with the *-prefix-map options when cross compiling. In general you're after to remap filenames for use in target context but the local paths should be used to find include files at co

Re: [PATCH v2] RISC-V: No extensions for SImode min/max against safe constant

Applied to master. Thanks! --Philipp. On Fri, 18 Nov 2022 at 21:11, Jeff Law wrote: > > On 11/8/22 17:06, Philipp Tomsich wrote: > > Optimize the common case of a SImode min/max against a constant > > that is safe both for sign- and zero-extension. > > E.g., consider the case > >int f(unsign

Re: [PATCH] RISC-V: Optimise adding a (larger than simm12) constant

On 11/9/22 16:07, Philipp Tomsich wrote: Handling the register-const_int addition has very quickly escalated to creating a full sign-extended 32bit constant and performing a register-register for RISC-V in GCC so far, resulting in sequences like (for the case of "a + 2048"): li a5,

Re: [PATCH] RISC-V: Optimise adding a (larger than simm12) constant

On Fri, 18 Nov 2022 at 22:13, Jeff Law wrote: > > > On 11/9/22 16:07, Philipp Tomsich wrote: > > Handling the register-const_int addition has very quickly escalated to > > creating a full sign-extended 32bit constant and performing a > > register-register for RISC-V in GCC so far, resulting in seq

[PATCH] c++: cache the normal form of a concept-id

We already cache the overall normal form of a declaration's constraints under the assumption that it can't change over the translation unit. But if we have two constrained declarations such as template void f() requires expensive && A; template void g() requires expensive && B; then despite t

[PATCH] c++: remove coerce_innermost_template_parms

IIUC the only practical difference between coerce_innermost_template_parms and the main function coerce_template_parms is that the former takes a multi-level template parameter list and returns a template argument vector of the same depth, whereas the latter takes a single-level template parameter

[committed] analyzer: move more impl_* to known_function

Fix a missing check that the argument to __analyzer_dump_capacity must be a pointer type (which would otherwise lead to an ICE). Do so by using the known_function_manager rather than by doing lots of string matching. Do the same for many other functions. Doing so moves the type-checking closer t

Re: [PATCH] RISC-V: Optimise adding a (larger than simm12) constant

On 11/18/22 14:26, Philipp Tomsich wrote: On Fri, 18 Nov 2022 at 22:13, Jeff Law wrote: On 11/9/22 16:07, Philipp Tomsich wrote: Handling the register-const_int addition has very quickly escalated to creating a full sign-extended 32bit constant and performing a register-register for RISC-V

nvptx: In 'STARTFILE_SPEC', fix 'crt0.o' for '-mmainkernel' (was: [MentorEmbedded/nvptx-tools] Match standard 'ld' "search" behavior (PR #38))

Hi! Re : On 2022-11-18T11:05:23-0800, I wrote: > Actually, in GCC/nvptx target testing, this #38's commit > 886a95faf66bf66a82fc0fe7d2a9fd9e9fec2820 "ld: Don't search for input files in > '-L'directories" is generall

Re: [PATCH] c++: remove coerce_innermost_template_parms

On 11/18/22 16:59, Patrick Palka wrote: IIUC the only practical difference between coerce_innermost_template_parms and the main function coerce_template_parms is that the former takes a multi-level template parameter list and returns a template argument vector of the same depth, whereas the latte

[PATCH v2] c++: Reject UDLs in certain contexts [PR105300]

On Thu, Nov 17, 2022 at 07:06:34PM -0500, Jason Merrill wrote: > On 11/16/22 20:12, Marek Polacek wrote: > > On Wed, Nov 16, 2022 at 08:22:39AM -0500, Jason Merrill wrote: > > > On 11/15/22 19:35, Marek Polacek wrote: > > > > On Tue, Nov 15, 2022 at 06:58:39PM -0500, Jason Merrill wrote: > > > > >

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