On Sat, 11 Feb 2023, incarnation.p@outlook.com wrote:
> From: Pan Li
>
> PR 108185
> PR 108654
>
> The bytesize of the vbool*_t isn't well defined. This patch
> adjust the rvv bool modes with actually mode size in bytes.
> However, only allow mode tieable when
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmsgt_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmsgt_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmsgt_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmsgt_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmsle_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmsle_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmsle_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmsle_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmslt_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmslt_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmslt_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmslt_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmsne_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmsne_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmsne_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmsne_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/predicates.md (vector_mask_operand): Refine the codes.
(vector_all_trues_mask_operand): New predicate.
(vector_undef_operand): New predicate.
(ltge_operator): New predicate.
On 2/10/23 15:41, Philipp Tomsich wrote:
Some architectures, as it the case on RISC-V with the proposed
ZiCondOps and the vendor-defined XVentanaCondOps, define a
conditional-zero instruction that is equivalent to:
- the positive form: rd = (rc != 0) ? rs : 0
- the negated form: rd =
On 1/28/23 11:16, Jonathan Yong via Gcc-patches wrote:
Patch OK?
gcc/testsuite/ChangeLog:
* gcc.dg/pr65658.c: fix LLP64 test.
0001-pr65658.c-fix-excess-warnings-on-LLP64-targets.patch
From bd2634e2795723f290dcf4bbb06e70fb6ca6af51 Mon Sep 17 00:00:00 2001
From: Jonathan
On 2/7/23 03:29, Richard Sandiford via Gcc-patches wrote:
In this PR we had a write to one vector of a 4-vector tuple.
The vector had mode V1DI, and the target doesn't provide V1DI
moves, so this was converted into:
(clobber (subreg:V1DI (reg/v:V4x1DI 92 [ b ]) 24))
followed by a
On 2/3/23 02:15, Richard Sandiford via Gcc-patches wrote:
aarch64/fcsel_1.c contains:
double
f_2 (double a, double b, double c, double d)
{
if (a > b)
return c;
else
return d;
}
which started failing in the GCC 12 timeframe. When it passed,
the RTL had the form:
[A]
On 1/31/23 18:21, Andrew Pinski via Gcc-patches wrote:
For bool values, it is easier to deal with
xor 1 rather than having 1 - a. This is because
we are more likely to simplify the xor further in many
cases.
This is a special case for (MASK - b) where MASK
is a powerof2 - 1 and b <= MASK but
On Fri, 3 Feb 2023 at 12:46, Prathamesh Kulkarni
wrote:
>
> Hi Richard,
> While digging thru aarch64_expand_vector_init, I noticed it gives
> priority to loading a constant first:
> /* Initialise a vector which is part-variable. We want to first try
> to build those lanes which are
On 2/11/23 01:33, Jonathan Yong via Gcc-patches wrote:
Attached patch OK?
0001-builtin-declaration-mismatch-7-fix-LLP64-targets.patch
From 3ba6812366e837a87c15360e83d1f72ffdd29684 Mon Sep 17 00:00:00 2001
From: Jonathan Yong<10wa...@gmail.com>
Date: Sat, 11 Feb 2023 08:30:55 +
Subject:
Hi,
Compare with previous version:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609654.html
This patch does not use UNSPEC for insn mtvsrws anymore. And to handle
the subreg better on BE and LE, predicate "lowpart_subreg_operator"
is introducted. To help combine pass to match the
committed :)
On Sun, Feb 12, 2023 at 10:42 PM wrote:
>
> LGTM
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-02-12 19:33
> To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong
> CC: Kito Cheng
> Subject: [PATCH] RISC-V: Handle vlenb correctly in unwinding
>
Hi,
Compare with previous version:
https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611513.html
This patch remove un-needed lowpart_subreg_operand.
For code:
```
u64
test_rlwinm_lowpart_mask (u32 v)
{
u32 v1 = ((v << N) | (v >> (32 - N))) & 0xf00;
return (u64)v1;
}
```
We generate
On Sat, Feb 11, 2023 at 12:18 AM Dan Li wrote:
>
> On 02/09, Hongtao Liu wrote:
> > On Mon, Dec 19, 2022 at 3:59 PM Dan Li via Gcc-patches
> > wrote:
> > >
> > > This series of patches is mainly used to support the control flow
> > > integrity protection of the linux kernel [1], which is similar
Pushed.
Gerald
libstdc++-v3/ChangeLog:
* doc/xml/manual/containers.xml: Tweak a link to N1780
(C++ standard).
* doc/html/manual/associative.html: Regenerate.
---
libstdc++-v3/doc/html/manual/associative.html | 2 +-
libstdc++-v3/doc/xml/manual/containers.xml| 2 +-
Hi Rimvydas,
> Gesendet: Sonntag, 12. Februar 2023 um 07:59 Uhr
> Von: "Rimvydas Jasinskas"
> An: "Harald Anlauf"
> Cc: "fortran"
> Betreff: Re: Support for NOINLINE attribute
>
> On Sat, Feb 11, 2023 at 11:26 PM Harald Anlauf wrote:
> > I am also not a native speaker, like many others
Here is a fix for PR105660.
Bootstrapped and regression tested on x86-64.
Fix ICE related to implicit access attributes for VLA arguments [PR105660]
When constructing the specifier string when merging an access attribute
that encodes information about VLA arguments, the
LGTM
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-02-12 19:33
To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH] RISC-V: Handle vlenb correctly in unwinding
gcc/ChangeLog:
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
This has been broken for years (if not forever), both when it comes
to onlinedocs and local installations.
Pushed.
Gerald
gcc/ChangeLog:
* doc/sourcebuild.texi: Remove (broken) direct reference to
"The GNU configure and build system".
---
gcc/doc/sourcebuild.texi | 3 +--
1
Committed, thanks :)
On Fri, Feb 3, 2023 at 5:45 PM Jin Ma via Gcc-patches
wrote:
>
> The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain
> potential risks:
>
> When the architecture adds pre-processing to `define_insn "adddi3"`, such as
> `define_expend "adddi3"`, the
gcc/ChangeLog:
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
(DWARF_FRAME_REGISTERS): New.
(DWARF_REG_TO_UNWIND_COLUMN): New.
libgcc/ChangeLog:
* config.host (riscv*-*-*): Add config/riscv/value-unwind.h.
* config/riscv/value-unwind.h: New.
---
Pushed.
Gerald
www.unix.org now redirects to unix.org.
libstdc++-v3/ChangeLog:
* doc/xml/manual/ctype.xml: Change www.unix.org to unix.org.
* doc/html/manual/facets.html: Regenerate.
---
libstdc++-v3/doc/html/manual/facets.html | 4 ++--
libstdc++-v3/doc/xml/manual/ctype.xml
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