Thanks Jeff for comments.
It makes sense to me. For the EQ operator we should have CONSTM1. Does this
mean s390 parts has similar issue here? Then for instructions like VMSEQ, we
need to adjust the simplify_rtx up to a point.
Please help to correct me if any mistake. Thank you again.
Pan
On 4/16/23 07:20, Ajit Agarwal wrote:
Hello All:
This patch improves code sinking pass to sink the blocks before calls
in the use blocks or immediate dominator blocks that reduces register pressure.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
tree-ssa-s
On Fri, 28 Apr 2023, Jeff Law wrote:
> On 4/28/23 16:42, Hans-Peter Nilsson wrote:
> > On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
> > I don't see anything in those functions that checks if
> > ZERO_EXTEND is actually a feature of the ABI, e.g. as opposed to
> > no extension or SIGN_EX
There is no canonical form for this case defined. So the aarch64 backend needs
a pattern to match both of these forms.
The forms are:
(set (reg/i:SI 0 x0)
(if_then_else:SI (eq (reg:CC 66 cc)
(const_int 0 [0]))
(reg:SI 97)
(const_int -1 [0x])))
and
(s
On 4/28/23 16:42, Hans-Peter Nilsson wrote:
On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
Hello All:
This new version of patch 4 use improve ree pass for rs6000 target using
defined ABI interfaces.
Bootstrapped and regtested on power64-linux-gnu.
Thanks & Regards
Ajit
OpenMP 5.0 removed the restriction that multiple collapsed loops must
be perfectly nested, allowing "intervening code" (including nested
BLOCKs) before or after each nested loop. In GCC this code is moved
into the inner loop body by the respective front ends.
In the Fortran front end, most of the
OpenMP 5.0 removed the restriction that multiple collapsed loops must
be perfectly nested, allowing "intervening code" (including nested
BLOCKs) before or after each nested loop. In GCC this code is moved
into the inner loop body by the respective front ends.
This patch changes the C++ front end
OpenMP 5.0 removed the restriction that multiple collapsed loops must
be perfectly nested, allowing "intervening code" (including nested
BLOCKs) before or after each nested loop. In GCC this code is moved
into the inner loop body by the respective front ends.
This patch changes the C front end to
OpenMP 5.0 removed the restriction that collapsed loops in "omp
for/do" and related constructs must be perfectly nested; it now allows
intervening code to appear before/after each nested loop level. The
spec allows implementations considerable freedom in how many times this
intervening code is exe
On 4/28/23 09:58, Hans-Peter Nilsson via Gcc-patches wrote:
Ok to commit?
-- >8 --
I tried to make use of check-function-bodies for cris-elf and was a
bit surprised to see it failing. There's a deliberate empty line
after the filled delay slot of the return-function which was
mishandled. I t
On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
> Hello All:
>
> This new version of patch 4 use improve ree pass for rs6000 target using
> defined ABI interfaces.
> Bootstrapped and regtested on power64-linux-gnu.
>
> Thanks & Regards
> Ajit
>
>
> ree: Improve ree pass for rs6
On 4/26/23 15:45, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-protos.h
(riscv_vector_preferred_simd_mode): New.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(emit_vlmax
The RISC-V psABI pull request is at
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378 . Pointers to
Paul Kirth's corresponding LLVM patches are also there.
On Fri, Apr 28, 2023 at 2:42 PM Hans Boehm wrote:
> The concern with making the new behavior non-default is of course that the
>
On 4/26/23 15:45, Michael Collison wrote:
2023-04-24 Michael Collison
Juzhe Zhong
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(riscv_vec
On 4/26/23 15:45, Michael Collison wrote:
2023-03-02 Michael Collison
Juzhe Zhong
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
*
On 4/20/23 15:03, Ajit Agarwal wrote:
Currently I support AND with const1_rtx. This is what is equivalent to zero
extension instruction in power instruction set. When you specify many other
constants and Could you please specify what other constants needs to be
supported and how to determ
On Fri, Apr 28, 2023 at 09:35:49AM +0100, Jonathan Wakely wrote:
> Yes, for both, thanks for the fix.
>
> After it lands on the gcc-13 branch I'll also update the manual with:
>
> --- a/libstdc++-v3/doc/xml/manual/abi.xml
> +++ b/libstdc++-v3/doc/xml/manual/abi.xml
> @@ -275,6 +275,7 @@ compatibl
On 4/6/23 19:37, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add auto-vectorization testing.
* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgrou
On 4/6/23 21:37, shiyul...@iscas.ac.cn wrote:
From: yulong
This patch fixes the problem of the contracts-tmpl-spec2.c running failure.
When run the dejagnu test, I find that the output is inconsistent with that
verified
in the testcase. So I try to modify it, and then it can be passed.
gcc
On 4/12/23 07:18, shiyul...@iscas.ac.cn wrote:
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in types.h that be included by stdio.h.
Thanks to Jeff Law for reviewing the previous version.
gcc/testsui
On 4/28/23 09:21, Pan Li via Gcc-patches wrote:
From: Pan Li
When some RVV integer compare operators act on the same vector registers
without mask. They can be simplified to VMSET.
This PATCH allows the eq, le, leu, ge, geu to perform such kind of the
simplification by adding one macro in r
The concern with making the new behavior non-default is of course that the
generated code will eventually end up on an A.7-capable platform.
An A.6-classic option for compiling code that will never run on a newer
machine seems OK. But I'm not sure that seq_cst stores are dynamically
frequent enoug
On 4/20/23 09:56, Jeff Law via Gcc-patches wrote:
On 1/17/23 15:59, Vineet Gupta wrote:
This could be useful for library writers who want to write code variants
for fast vs. slow unaligned accesses.
We distinguish explicit -mstrict-align (1) vs. slow_unaligned_access
cpu tune param (2) for
On 4/21/23 04:07, Fei Gao wrote:
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without save-restore,
less stack memory can be reserved. This patch decouples stack allocation for
rv32e w/o save-restore and makes r
GCC_11.0 is an aarch64-specific outlier.
* doc/xml/manual/abi.xml (abi.versioning.history): Add
GCC_7.0.0, GCC_9.0.0, GCC_11.0, GCC_12.0.0, GCC_13.0.0 for
libgcc_s.
---
libstdc++-v3/doc/xml/manual/abi.xml | 5 +
1 file changed, 5 insertions(+)
diff --git a/libstdc++-
On 4/28/23 10:10, Robin Dapp wrote:
Hi,
I figured I'm going to start sending some patches that build on top
of the upcoming RISC-V autovectorization. This one is obviously
not supposed to be installed before the basic support lands but
it's small enough that it shouldn't hurt to send it now.
On 2/17/23 07:02, Matevos Mehrabyan via Gcc-patches wrote:
Hi all,
If we have division and remainder calculations with the same operands:
a = b / c;
d = b % c;
We can replace the calculation of remainder with multiplication +
subtraction, using the result from the previous division:
Kito and I were talking this morning, he's going to try and find the
time to actually write this. Kind of odd to send to the mailing list,
but I figure that's the easist way to get it out. It's very much not
mergeable as is...
---
gcc/doc/invoke.texi | 87
On Fri, 28 Apr 2023, Patrick Palka wrote:
> On Fri, 28 Apr 2023, Patrick Palka wrote:
>
> > After mechanically replacing RESULT_DECL within a constexpr call result
> > (for sake of RVO), we can in some cases simplify the call result
> > further.
> >
> > In the below testcase the result of get()
On Fri, 28 Apr 2023, Patrick Palka wrote:
> After mechanically replacing RESULT_DECL within a constexpr call result
> (for sake of RVO), we can in some cases simplify the call result
> further.
>
> In the below testcase the result of get() during evaluation of a's
> initializer is the self-refere
After mechanically replacing RESULT_DECL within a constexpr call result
(for sake of RVO), we can in some cases simplify the call result
further.
In the below testcase the result of get() during evaluation of a's
initializer is the self-referential CONSTRUCTOR:
{._M_p=(char *) &._M_local_buf}
On 4/27/23 08:29, Karen Sargsyan via Gcc-patches wrote:
clmul[h] instructions were added only for the ZBKC extension.
This patch includes them in the ZBC extension too.
Besides, added support of 'clmulr' instructions for ZBC extension.
gcc/ChangeLog:
* config/riscv/bitmanip.md: Added cl
We're certainly pushing for the same ABI (A.6 + trailing fence on store) in
LLVM as well. I'm about to upload a pull request for the psABI document
that describes this version of the ABI, and a bit of the rationale for it.
I'll attach the current draft here.
I agree that compatibility is critical
On 28 April 2023 09:26:06 CEST, Tobias Burnus wrote:
>Committed as r14-319-g7ebd4a1d61993c0a75e9ff3098aded21ef04a4da
> Only other changes are fixing the variable name a(b)breviated_modproc_decl
I think this is not good, I've mentioned it somewhere, i think, but I'll rename
it.
thanks!
On 28 April 2023 11:23:55 CEST, Florian Weimer via Fortran
wrote:
>* Martin Liška:
>But that's okay for me as well.
Even better.
On 4/28/23 10:44, Patrick O'Neill wrote:
On 4/28/23 09:29, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
...
LLVM mapping notes
LLVM emits corresponding fences for atomic_signal_fence instructio
On 4/27/23 10:23, Patrick O'Neill wrote:
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New
On 4/27/23 10:23, Patrick O'Neill wrote:
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
OK.
jeff
On 4/27/23 10:22, Patrick O'Neill wrote:
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (mem_thread_fence_1): Change fence
d
On 4/27/23 10:22, Patrick O'Neill wrote:
Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs
as needed.
Atomic compare and exchange ops provide success and failure memory
models. C++17 and later place no restrictions on the relative strength
of each model, so ensure we cov
PR target/105525 is a build regression for the vax and lm32 linux
targets present in gcc-12/13/head, where the builds fail due to
unsatisfied references to __INTPTR_TYPE__ and __UINTPTR_TYPE__,
caused by these two targets failing to provide glibc-stdint.h.
Fixed thusly, tested by building crosses,
On 4/28/23 09:29, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
htt
On Fri, 28 Apr 2023 10:40:15 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'N
On 4/27/23 10:22, Patrick O'Neill wrote:
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
Should be "PR target/89835"
gcc/ChangeLog:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): change behavior
of %A to include release bits.
Capitalize "change" in the ChangeLog en
Hi Kwok,
On 17.02.23 12:45, Kwok Cheung Yeung wrote:
This is a revised version of the patch for the 'present' modifier for
OpenMP. Compared to the first version, three improvements have been made:
- A bug which caused bootstrapping with a '-m32' multilib on x86-64 to
fail due to pointer size is
On 4/27/23 10:22, Patrick O'Neill wrote:
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Chan
These two patches implement the base support of builtin_zero_pattern
into match.pd. To implement the other part requires match-and-simplify
inside phiopt to support moving 2 statements from the middle-bb. The
match.pd part is already incldued. I will try to get to it next week.
Also __builtin_clr
This adds the patterns for
POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
For "a != 0 ? FUNC(a) : CST".
CLRSB, CLRSBL, and CLRSBLL will be moved next.
Note this is not enough to remove
cond_removal_in_builtin_zero_pattern as we need to handle
the case where there is an NOP_CONVERT inside the conditional
t
While moving working on moving
cond_removal_in_builtin_zero_pattern to match, I noticed
that functions were not allowed to move as we reject all
non-assignments.
This changes to allowing a few calls which are known not
to throw/trap. Right now it is restricted to ones
which cond_removal_in_builtin_
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation
> fixes
>
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
>
> From:
On 4/28/23 10:43, Palmer Dabbelt wrote:
On Fri, 28 Apr 2023 08:20:24 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 01:39, Jan Beulich via Gcc-patches wrote:
On 26.04.2023 17:45, Palmer Dabbelt wrote:
On Wed, 26 Apr 2023 08:26:26 PDT (-0700), gcc-patches@gcc.gnu.org
wrote:
On 4/2
On 4/27/23 10:22, Patrick O'Neill wrote:
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
libgcc/ChangeLog:
* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
sequentially consistent LR
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 06/10] arm: Fix overloading of MVE scalar constant
> parameters on vbicq
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic
>
> From: Stam
Hi Andrea, Stam,
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Stam Markianos-Wright wri...@arm.com>
> Subject: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting
On Fri, 28 Apr 2023 08:20:24 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 01:39, Jan Beulich via Gcc-patches wrote:
On 26.04.2023 17:45, Palmer Dabbelt wrote:
On Wed, 26 Apr 2023 08:26:26 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 4/25/23 08:50, Jan Beulich via Gcc-patches wrot
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Andrea Corallo
> Subject: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
>
> Hi all,
>
> this patch improves a nu
On Fri, 28 Apr 2023 09:14:00 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
https://github.com/riscv/riscv-isa-manual/bl
> -Original Message-
> From: Andrea Corallo
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Andrea Corallo
> Subject: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
>
> Hi all,
>
> this patch fixes the vstrwq* MVE
On 4/27/23 10:22, Patrick O'Neill wrote:
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
OK. Not s
On 4/27/23 10:22, Patrick O'Neill wrote:
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157
Hi,
I figured I'm going to start sending some patches that build on top
of the upcoming RISC-V autovectorization. This one is obviously
not supposed to be installed before the basic support lands but
it's small enough that it shouldn't hurt to send it now.
This patch allows vector constants in r
On 25/04/2023 13:30, Richard Biener wrote:
On Mon, 24 Apr 2023, Richard Sandiford wrote:
Richard Biener writes:
On Thu, Apr 20, 2023 at 3:24?PM Andre Vieira (lists) via Gcc-patches
wrote:
Rebased all three patches and made some small changes to the second one:
- removed sub and abd opta
Ok to commit?
-- >8 --
I tried to make use of check-function-bodies for cris-elf and was a
bit surprised to see it failing. There's a deliberate empty line
after the filled delay slot of the return-function which was
mishandled. I thought "aha" and tried to add an empty line
(containing just a "*
From: Pan Li
When some RVV integer compare operators act on the same vector registers
without mask. They can be simplified to VMSET.
This PATCH allows the eq, le, leu, ge, geu to perform such kind of the
simplification by adding one macro in riscv for simplify rtx.
Given we have:
vbool1_t test_
On 4/27/23 01:39, Jan Beulich via Gcc-patches wrote:
On 26.04.2023 17:45, Palmer Dabbelt wrote:
On Wed, 26 Apr 2023 08:26:26 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 4/25/23 08:50, Jan Beulich via Gcc-patches wrote:
RISC-V will emit ".option nopic" when -fno-pie is in effect, which
On 4/28/23 06:29, Jivan Hakobyan via Gcc-patches wrote:
RV64 the following code:
unsigned Min(unsigned a, unsigned b) {
return a < b ? a : b;
}
Compiles to:
Min:
zext.w a1,a1
zext.w a0,a0
minua0,a1,a0
sext.w a0,a0
ret
This patch
Pushed to master as obvious.
Martin
contrib/ChangeLog:
* filter_gcc_for_doxygen: Use python3 and not python2.
* filter_params.py: Likewise.
---
contrib/filter_gcc_for_doxygen | 2 +-
contrib/filter_params.py | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --
> On the check for verbose==2, should that be verbose >= 2 ?
>
That's fair enough. Made the change.
Thanks,
Tamar.
> paul
>
> > On Apr 28, 2023, at 6:38 AM, Tamar Christina via Gcc-patches patc...@gcc.gnu.org> wrote:
> >
> > Hi All,
> >
> > genmatch currently outputs commented out line
On the check for verbose==2, should that be verbose >= 2 ?
paul
> On Apr 28, 2023, at 6:38 AM, Tamar Christina via Gcc-patches
> wrote:
>
> Hi All,
>
> genmatch currently outputs commented out line directives that have no effect
> but the compiler still has to parse only to discard.
>
speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.
gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
Jiaxun Yang 于2023年4月28日周五 20:36写道：
>
>
>
> > 2023年4月28日 13:33，YunQiang Su 写道：
> >
> > speculation_barrier for MIPS needs sync+jr.hb (r2+),
> > so we implement __speculation_barrier in libgcc, like arm32 does.
> >
> > gcc/ChangeLog:
> > * config/mips/mips-protos.h (mips_emit_speculation_barrier):
Cool, Thank you!
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, April 28, 2023 8:37 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR
pushed, thanks!
On 26/04/23 20:06 +0100, Jonathan Wakely wrote:
On 26/04/23 09:53 -0700, Andrew Pinski wrote:
This adds a note about iostream usage so it does not catch others
in surpise like it has already.
OK?
Thanks, I agree we should add something, but have some comments below.
---
htdocs/gcc-13/change
Hi Julian!
On 2023-04-27T11:36:47-0700, Julian Brown wrote:
> This patch fixes several cases where multiple attach or detach mapping
> nodes were being created for stand-alone attach or detach clauses
> in Fortran. After the introduction of stricter checking later during
> compilation, these ext
On Thu, 27 Apr 2023, Patrick Palka wrote:
> On Thu, Apr 27, 2023 at 4:46 PM Patrick Palka wrote:
> >
> > Now that with r14-11-g2245459c85a3f4 made us coerce the template
> > arguments of a bound ttp again after level-lowering, this unfortunately
> > causes a crash from coerce_template_args_for_tt
This patch replaces the existing tree_code widen_plus and widen_minus
patterns with internal_fn versions.
DEF_INTERNAL_OPTAB_HILO_FN is like DEF_INTERNAL_OPTAB_FN except it
provides convenience wrappers for defining conversions that require a
hi/lo split, like widening and narrowing operations.
This adds a scatter vectorization capability to the vectorizer
without target support by decomposing the offset and data vectors
and then performing scalar stores in the order of vector lanes.
This is aimed at cases where vectorizing the rest of the loop
offsets the cost of vectorizing the scatter.
Hi,
I'm posting the patches separately now with ChangeLogs.
I made the suggested changes and tried to simplify the code a bit
further. Where internal to tree-vect-stmts I changed most functions to
use code_helper to avoid having to check at places we didn't need to. I
was trying to simplify t
This is a rebase of Joel's previous patch.
This patch removes the old widen plus/minus tree codes which have been
replaced by internal functions.
gcc/ChangeLog:
2023-04-28 Andre Vieira
Joel Hutton
* doc/generic.texi: Remove old tree codes.
* expr.cc (expand_exp
On Fri, 28 Apr 2023, Tamar Christina wrote:
> > > [1] https://gcc.gnu.org/legacy-ml/gcc-patches/2018-04/msg01125.html
> > >
> > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
> > >
> > > Ok for master?
> >
> > Some comments - I have to leave the Makefile bits to somebody else t
> 2023年4月28日 13:33，YunQiang Su 写道：
>
> speculation_barrier for MIPS needs sync+jr.hb (r2+),
> so we implement __speculation_barrier in libgcc, like arm32 does.
>
> gcc/ChangeLog:
> * config/mips/mips-protos.h (mips_emit_speculation_barrier): New
>prototype.
> * config/mips/mips.cc (sp
pushed, thanks!
speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.
gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
RV64 the following code:
unsigned Min(unsigned a, unsigned b) {
return a < b ? a : b;
}
Compiles to:
Min:
zext.w a1,a1
zext.w a0,a0
minua0,a1,a0
sext.w a0,a0
ret
This patch removes unnecessary zero extensions of minu/maxu operands.
gcc/Chang
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
This avoids showing absolute paths from the expansion of
@srcdir@/libsupc++/ in the doxygen File List view.
libstdc++-v3/ChangeLog:
* doc/doxygen/user.cfg.in (STRIP_FROM_PATH): Remove prefixes
from header paths.
---
libstdc++-
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* include/bits/uses_allocator.h: Add missing @file comment.
* include/bits/regex.tcc: Remove stray doxygen comments.
* include/experimental/memory_resource: Likewise.
* include/std/bit: Tw
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
Add @headerfile and @since tags. Add gamma_distribution to the correct
group (poisson distributions). Add a group for the sampling
distributions and add the missing definitions of their probability
functions. Add uniform_int_distribution back to
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
There's no good reason to conditionally close and reopen namespace std
within an #if block. Just include the header at the top
instead.
libstdc++-v3/ChangeLog:
* include/bits/move.h: Simplify opening/closing namespace std.
---
libstd
On Fri, 28 Apr 2023, Tamar Christina wrote:
> Hi All,
>
> In preparation for automatically splitting match.pd files I split off the
> non-static helper functions that are shared between the match.pd functions off
> to another file.
>
> This file can be compiled in parallel and also allows us to
On Fri, 28 Apr 2023, Tamar Christina wrote:
> Hi All,
>
> This is a small improvement in QoL codegen for match.pd to save time not
> re-evaluating the condition for printing debug information in every function.
>
> There is a small but consistent runtime and compile time win here. The
> runtim
On Fri, 28 Apr 2023, Tamar Christina wrote:
> Hi All,
>
> genmatch currently outputs commented out line directives that have no effect
> but the compiler still has to parse only to discard.
>
> They are however handy when debugging genmatch output. As such this moves
> them
> behind the -vv fl
On Fri, Apr 28, 2023 at 12:29:58PM +0100, Richard Sandiford wrote:
> Jakub Jelinek via Gcc-patches writes:
> > Hi!
> >
> > On Thu, Apr 27, 2023 at 10:34:59AM +, Richard Biener wrote:
> >> OK. As said the patch itself looks good to me, let's go ahead. We
> >> have plenty of time to backtrack u
There's another questionable IL transform by IPA SRA, replacing
foo (p_1(D)->x) with foo (VIEW_CONVERT (ISRA.PARM.1))
where ISRA.PARM.1 is a register. Conversion of a register to
an aggregate type is questionable but not entirely unreasonable
and not within the set of IL I am rejecting when fixin
From: Stam Markianos-Wright
These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:
* The #shift immediate value not in the check-function-bodies as expected
* Some shifts getting optimised to mov immediates, e.g.
`uqshll (1, 1);` -> movsr0
Hi all,
this patch fixes the vstrwq* MVE instrinsics failing to emit the
correct sequence of instruction due to a missing predicates. Also the
immediate range is fixed to be multiples of 2 up between [-252, 252].
Best Regards
Andrea
gcc/ChangeLog:
* config/arm/constraints.md (mve_vld
From: Stam Markianos-Wright
Hi all,
We noticed that calls to the vadcq and vsbcq intrinsics, both of
which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
the FPSCR, would produce the following code:
```
< r2 is the *carry input >
vmrsr3, FPSCR_nzcvqc
bic r3, r3, #536870912
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