On Fri, 12 May 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> We are running out of the machine_mode(8 bits) in RISC-V backend. Thus
> we would like to extend the machine mode bit size from 8 to 16 bits.
> However, it is sensitive to extend the memory size in common structure
> like tree or r
Committed to trunk.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Friday, May 12, 2023 2:32 PM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; pal...@dabbelt.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Fix
> ok, thanks :)
This has likely been discussed at length before, but why need to
specify the additional -mabi with -march (instead of -march implying
a matching abi)?
ok
On Fri, May 12, 2023 at 11:11 AM wrote:
>
> From: Juzhe-Zhong
>
> After update local codebase to the trunk. I realize there is one more fail in
> RV32.
> After this patch, all fails of RVV are cleaned up.
> Thanks.
>
> FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c -O3 -ftree-vectorize (t
On Thu, May 11, 2023 at 4:21 PM Roger Sayle wrote:
>
>
> PR 109766 is an interesting case of large code being generated on x86_64,
> caused by an interaction/conflict between register allocation and hardreg
> cprop, that's tricky to fix/resolve within the middle-end.
>
> The task/challenge is to p
On Fri, May 12, 2023 at 1:50 PM Andrew Pinski wrote:
>
> On Thu, May 11, 2023 at 10:45 PM liuhongt via Gcc-patches
> wrote:
> >
> > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> > Ok for trunk?
> >
> > gcc/ChangeLog:
> >
> > PR target/89701
> > * common.opt: Refactor
This patch allows mips16e2 acts the same with -O1~3
when generating ZEB/ZEH instead of ANDI under
the -O0 option, which shrinks the code size.
gcc/ChangeLog:
* config/mips/mips.md(*and3_mips16): Generates
ZEB/ZEH instructions.
---
gcc/config/mips/mips.md | 30 +
There are shortened bitwise instructions in the mips16e2 ASE,
for instance, ANDI, ORI/XORI, EXT, INS etc. .
This patch adds these instrutions with corresponding tests.
gcc/ChangeLog:
* config/mips/constraints.md(Yz): New constraints for mips16e2.
* config/mips/mips-protos.h(mips_
This patch adds LWL/LWR, SWL/SWR instructions with their
corresponding tests.
gcc/ChangeLog:
* config/mips/mips.cc(mips_expand_ins_as_unaligned_store):
Add logics for generating instruction.
* config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2.
*
This patch adds LUI instruction from mips16e2
with corresponding test.
gcc/ChangeLog:
* config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction.
(mips_const_insns): Same as above.
(mips_output_move): Same as above.
(mips_output_function_prologue): Same
The mips16e2 ASE uses eight general-purpose registers
from mips32, with some special-purpose registers,
these registers are GPRs: s0-1, v0-1, a0-3, and
special registers: t8, gp, sp, ra.
As mentioned above, the special register gp is
used in mips16e2, which is the global pointer register,
it is us
This patch adds MOVx instructions from mips16e2
(movn,movz,movtn,movtz) with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for
ISA_HAS_MIPS16E2.
* config/mips/mips.md(*mov_on_): Add logics for
MOVx insts.
(*mov_on__mips16e2): G
The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
This series of patches adds all instructions of MIPS16E2 ASE.
Jie Mei (9):
MIPS: Add basic support for mips16e2
MIPS: Add MOVx instructions support for mips16e2
MIPS: Add inst
This patch adds CACHE instruction from mips16e2
with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.c(mips_9bit_offset_address_p): Restrict the
address register to M16_REGS for MIPS16.
(BUILTIN_AVAIL_MIPS16E2): Defined a new macro.
(AVAIL_MIPS16E2_OR_NON_MI
The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
It defines new special instructions for increasing
code density (e.g. Extend, PC-relative instructions, etc.).
This patch adds basic support for mips16e2 used by the
following series
The MIPS16e2 ASE has PREF, LL and SC instructions,
they use 9 bits immediate, like mips32r6.
The MIPS32 PRE-R6 uses 16 bits immediate.
gcc/ChangeLog:
* config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
for ISA_HAS_MIPS16E2.
(ISA_HAS_SYNC): Same as above.
(I
> The vector shift immediates happen to have the same constraints as some
> of the CSR-related operands, but it's a different usage. This adds a
> name for them, so I don't get confused again next time.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (shifts): Use
> vector_scalar_
On Thu, May 11, 2023 at 5:20 PM Cui, Lili wrote:
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Thursday, May 11, 2023 6:53 PM
> > To: Cui, Lili
> > Cc: gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH 1/2] PR gcc/98350:Add a param to control the length of
> > the chain with
On Thu, May 11, 2023 at 10:45 PM liuhongt via Gcc-patches
wrote:
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/89701
> * common.opt: Refactor -fcf-protection= to support combination
> of param.
> * lto
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
PR target/89701
* common.opt: Refactor -fcf-protection= to support combination
of param.
* lto-wrapper.c (merge_and_complain): Adjusted.
* opts.c (parse_cf_protection_opt
On Wed, May 10, 2023 at 5:10 PM liuhongt wrote:
>
> > The quoted patch shows -shared in context and you didn't post a
> > backport version
> > to look at. But yes, we shouldn't change -shared behavior on a
> > branch, even less so make it
> > inconsistent between targets.
> Here's the patch.
>
>
From: Pan Li
We are running out of the machine_mode(8 bits) in RISC-V backend. Thus
we would like to extend the machine mode bit size from 8 to 16 bits.
However, it is sensitive to extend the memory size in common structure
like tree or rtx. This patch would like to extend the machine mode bits
t
Committed to trunk.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Friday, May 12, 2023 11:00 AM
To: 钟居哲
Cc: GCC Patches ; Palmer Dabbelt ;
Jeff Law ; Robin Dapp
Subject: Re: [PATCH V3] RISC-V: Add basic vec_init for VLS RVV
auto-vectorization
From: Juzhe-Zhong
After update local codebase to the trunk. I realize there is one more fail in
RV32.
After this patch, all fails of RVV are cleaned up.
Thanks.
FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c -O3 -ftree-vectorize (test
for excess errors)
Excess errors:
cc1: error: ABI requir
I have remove comments related to LLVM and reorg testcases:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618256.html
V3 can you take a look again.
Sorry for sending wrong comments in changelog. Well, I goal is not to disparage
LLVM.
I am just used to reading the LLVM implementation while s
Ok
於 2023年5月12日 週五 10:57 寫道：
> From: Juzhe-Zhong
>
> #include
>
> typedef int8_t vnx16qi __attribute__((vector_size (16)));
>
> #include
>
> typedef int8_t vnx16qi __attribute__ ((vector_size (16)));
> typedef int8_t vnx32qi __attribute__ ((vector_size (32)));
> typedef int8_t vnx64qi __attri
From: Juzhe-Zhong
#include
typedef int8_t vnx16qi __attribute__((vector_size (16)));
#include
typedef int8_t vnx16qi __attribute__ ((vector_size (16)));
typedef int8_t vnx32qi __attribute__ ((vector_size (32)));
typedef int8_t vnx64qi __attribute__ ((vector_size (64)));
typedef int8_t vnx128
From: Pan Li
1. This patch is moving binary autovec testcases into binop directory to
make it
easier to maintain.
2. Current binary autovec only tested in LMUL = 1, enable testing in
LMUL = 2/4/8.
Tested on both rv32/rv64, with no fails in RVV.
gcc/testsuite/ChangeLog:
* gcc.tar
From: Pan Li
In rv32:
FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize
(test for excess
> This patch makes vec_init support common init vector handling (using
> vslide1down to insert element)
> which can handle any cases of initialization vec but it's not optimal for
> cases.
>
> And support Case 1 optimizaiton:
> https://godbolt.org/z/Yb9PK9jsz
Don't use godbolt link in comment, b
ok, thanks :)
On Fri, May 12, 2023 at 9:04 AM juzhe.zh...@rivai.ai
wrote:
>
> This patch has tested on both RV32/RV64, and all fails in RVV are cleaned up.
> Ok for trunk?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-12 07:29
> To: gcc-patches
> CC: kito.cheng; palmer; jeffr
OK
On Fri, May 12, 2023 at 9:03 AM wrote:
>
> From: Juzhe-Zhong
>
> 1. This patch is moving binary autovec testcases into binop directory to make
> it
> easier to maintain.
>
> 2. Current binary autovec only tested in LMUL = 1, enable testing in LMUL =
> 2/4/8.
>
> Tested on both rv32/rv64, wi
From: Pan Li
The decl_or_value is defined as void * before this PATCH. It will take
care of both the tree_node and rtx_def. Unfortunately, given a void
pointer cannot tell the input is tree_node or rtx_def.
Then we have some implicit structure layout requirement similar as
below. Or we will touc
LGTM, thanks :)
Palmer Dabbelt 於 2023年5月12日 週五 06:32 寫道：
> The vector shift immediates happen to have the same constraints as some
> of the CSR-related operands, but it's a different usage. This adds a
> name for them, so I don't get confused again next time.
>
> gcc/ChangeLog:
>
> * co
From: Juzhe-Zhong
Rebase to trunk.
This is patching is adding basic vec_init support for RVV auto-vectorization.
This patch has been full coverage tested.
This patch makes vec_init support common init vector handling (using
vslide1down to insert element)
which can handle any cases of initializ
This patch has tested on both RV32/RV64, and all fails in RVV are cleaned up.
Ok for trunk?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-12 07:29
To: gcc-patches
CC: kito.cheng; palmer; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix RVV binary auto-vectorizaiton test fails
From:
From: Juzhe-Zhong
1. This patch is moving binary autovec testcases into binop directory to make it
easier to maintain.
2. Current binary autovec only tested in LMUL = 1, enable testing in LMUL =
2/4/8.
Tested on both rv32/rv64, with no fails in RVV.
Ok for trunk ?
gcc/testsuite/ChangeLog:
On Thu, 11 May 2023 at 21:20, Jonathan Wakely via Libstdc++ <
libstd...@gcc.gnu.org> wrote:
> Tested powerpc64le-linux. Pushed to trunk.
>
> I don't plan to backport the assertions, because they're an API change
> that isn't suitable for the branches. But removing _Alloc_traits_impl
> and replacin
From: Juzhe-Zhong
In rv32:
FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize (test
fo
From: Juzhe-Zhong
In rv32:
FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize (test
fo
Hi, Richards.
Could you take a look at this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618241.html
Thanks
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-11 20:42
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V4] VECT: Add decrement IV ite
From: Ju-Zhe Zhong
1. Fix document description according Jeff && Richard.
2. Add LOOP_VINFO_USING_SELECT_VL_P for single rgroup.
3. Add LOOP_VINFO_USING_SLP_ADJUSTED_LEN_P for SLP multiple rgroup.
Fix bugs for V5 after testing:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618209.html
gcc/
LGTM
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-12 06:31
To: juzhe.zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add v_uimm_operand
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zh...@rivai.ai wrote:
>>> ;; V has 32-bit unsigned immediates. This happens to be
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zh...@rivai.ai wrote:
;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt
should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR
related.
(define_predicate "v_uimm_operand"
(match_operand 0 "csr
The vector shift immediates happen to have the same constraints as some
of the CSR-related operands, but it's a different usage. This adds a
name for them, so I don't get confused again next time.
gcc/ChangeLog:
* config/riscv/autovec.md (shifts): Use
vector_scalar_shift_operan
>> ;; V has 32-bit unsigned immediates. This happens to be the same
>> constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand,
>> but it's not CSR related.
>> (define_predicate "v_uimm_operand"
>> (match_operand 0 "csr_operand"))
To make name consistent, it should be "vector
On Mon, 27 Mar 2023 at 22:25, Weslley da Silva Pereira via Libstdc++ <
libstd...@gcc.gnu.org> wrote:
> Dear all,
>
> Here follows a patch that removes implicit type casts in std::complex.
>
> *Description:* The current implementation of `complex<_Tp>` assumes that
> `int, double, long double` are
On Thu, 11 May 2023 at 21:25, Jason Merrill wrote:
> On 5/9/23 08:07, Alex Coplan wrote:
> > This patch implements clang's __has_feature and __has_extension in GCC.
>
> Thanks!
>
> > Currently the patch aims to implement all documented features (and some
> > undocumented ones) following the docum
On Thu, 11 May 2023 at 13:42, Jonathan Wakely wrote:
>
>
> On Thu, 11 May 2023 at 13:19, Mike Crowe wrote:
>
>> However, ...
>>
>> > > diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4
>> > > index 89e7f5f5f45..e2700b05ec3 100644
>> > > --- a/libstdc++-v3/acinclude.m4
>> > > +++
On Wed, 22 Mar 2023, Jonathan Wakely via Gcc-patches wrote:
> We don't currently have a single page where you can find out when
> support for a given standard became non-experimental (you have to look
> through all the gcc-X/changes.html pages to find it). I think we should
> have that info on the
On 5/9/23 08:07, Alex Coplan wrote:
This patch implements clang's __has_feature and __has_extension in GCC.
Thanks!
Currently the patch aims to implement all documented features (and some
undocumented ones) following the documentation at
https://clang.llvm.org/docs/LanguageExtensions.html wit
Tested powerpc64le-linux. Pushed to trunk.
Patrick noted that auto_ferounding could be used in floating_to_chars.cc
too, which I'll do later.
-- >8 --
This adds auto_locale and auto_ferounding types to use RAII for changing
and restoring the local and floating-point environment when using strtod
Tested powerpc64le-linux. Pushed to trunk.
This is a regression on gcc-13 too, but I'm undecided about the ABI
change for the branch. Generally that would be a no-go, but the affected
specializations are probably so rare that it would be OK. And we
definitely want to fix the ambiguity on the branc
Tested powerpc64le-linux. Pushed to trunk.
I don't plan to backport the assertions, because they're an API change
that isn't suitable for the branches. But removing _Alloc_traits_impl
and replacing it with _S_allocate should be done for gcc-13 to keep the
contents of the two libstdc++.so.6.0.32 li
Bootstrapped and reg-tested overnight for x86 and aarch64.
Applied to master, thanks!
Philipp.
On Tue, 9 May 2023 at 09:13, Richard Biener wrote:
>
> On Tue, Dec 20, 2022 at 1:23 PM Manolis Tsamis
> wrote:
> >
> > When using SWAR (SIMD in a register) techniques a comparison operation
> > with
On 5/11/23 14:30, Patrick Palka wrote:
r13-2701-g7107ea6fb933f1 made us correctly accept 'mutable' member
accesses during constexpr evaluation of objects constructed during that
evaluation, while continuing to reject such accesses for constexpr
objects constructed outside of that evaluation, by c
Tejas Belagod writes:
> From: Tejas Belagod
>
> This PR optimizes an SVE intrinsics sequence where
> svlasta (svptrue_pat_b8 (SV_VL1), x)
> a scalar is selected based on a constant predicate and a variable vector.
> This sequence is optimized to return the correspoding element of a NEON
Prathamesh Kulkarni writes:
> On Tue, 2 May 2023 at 18:22, Richard Sandiford
> wrote:
>>
>> Prathamesh Kulkarni writes:
>> > On Tue, 2 May 2023 at 17:32, Richard Sandiford
>> > wrote:
>> >>
>> >> Prathamesh Kulkarni writes:
>> >> > On Tue, 2 May 2023 at 14:56, Richard Sandiford
>> >> > wrote
Prathamesh Kulkarni writes:
> diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-18.c
> b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c
> new file mode 100644
> index 000..598a51f17c6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c
> @@ -0,0 +1,20 @@
> +/* { dg
Do not crash when asking ix86_widen_mult_cost for the cost of
a widening mul operation to V4HI or V2SImode.
gcc/ChangeLog:
PR target/109807
* config/i386/i386.cc (ix86_widen_mult_cost):
Handle V4HImode and V2SImode.
gcc/testsuite/ChangeLog:
PR target/109807
* gcc.target/i386
On Thu, 11 May 2023, Patrick Palka wrote:
> r13-2701-g7107ea6fb933f1 made us correctly accept 'mutable' member
> accesses during constexpr evaluation of objects constructed during that
> evaluation, while continuing to reject such accesses for constexpr
> objects constructed outside of that evalua
> Date: Thu, 11 May 2023 12:15:20 -0600
> From: Jeff Law
> On 5/11/23 10:55, Paul Koning wrote:
> >
> >
> >> On May 11, 2023, at 11:05 AM, Hans-Peter Nilsson via Gcc-patches
> >> wrote:
> >>
> >> ...
> >> Yes, very interesting. Thank you for sharing this. I've
> >> seen regressions with LRA
r13-2701-g7107ea6fb933f1 made us correctly accept 'mutable' member
accesses during constexpr evaluation of objects constructed during that
evaluation, while continuing to reject such accesses for constexpr
objects constructed outside of that evaluation, by considering the
CONSTRUCTOR_MUTABLE_POISON
The vector shift immediates happen to have the same constraints as some
of the CSR-related operands, but it's a different usage. This adds a
name for them, so I don't get confused again next time.
gcc/ChangeLog:
* config/riscv/autovec.md (shifts): Use v_uimm_operand.
* config/ris
On 5/11/23 10:55, Paul Koning wrote:
On May 11, 2023, at 11:05 AM, Hans-Peter Nilsson via Gcc-patches
wrote:
...
Yes, very interesting. Thank you for sharing this. I've
seen regressions with LRA for CRIS too, for
"double-register-sized" types, which for CRIS, a 32-bit
target, translate
"Roger Sayle" writes:
> This patch proposes adding run-time library support for bit reversal,
> by adding a __bitrevsi2 function to libgcc. Thoughts/opinions?
>
> I'm also tempted to add __popcount[qh]i2 and __parity[qh]i2 to libgcc,
> to allow the RTL optimizers to perform narrowing operations,
On Thu, 11 May 2023 07:21:30 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/11/23 04:33, Robin Dapp wrote:
"csr_operand" does seem wrong, though, as that just accepts constants.
Maybe "arith_operand" is the way to go? I haven't looked at the
V immediates though.
I was pondering changing the s
"Roger Sayle" writes:
> An analysis of backend UNSPECs reveals that two of the most common UNSPECs
> across target backends are for copysign and bit reversal. This patch
> adds RTX codes for these expressions to allow their representation to
> be standardized, and them to optimized by the middle-
> Am 11.05.2023 um 17:18 schrieb Andrew Pinski via Gcc-patches
> :
>
> While I was looking at differences before and after
> r14-569-g21e2ef2dc25de3, I noticed that one phi node was
> not being removed.
> For an example, while compiling combine.cc, in expand_field_assignment,
> we would remov
> On May 11, 2023, at 11:05 AM, Hans-Peter Nilsson via Gcc-patches
> wrote:
>
> ...
> Yes, very interesting. Thank you for sharing this. I've
> seen regressions with LRA for CRIS too, for
> "double-register-sized" types, which for CRIS, a 32-bit
> target, translates to 64-bit types (DFmode
As of https://go.dev/cl/476695 the package golang.org/x/sys/unix
expects a syscall.prlimit function to exist. This libgo patch adds
that function. This is for https://go.dev/issue/46279 and
https://go.dev/issue/59712. Since this is a small patch and is needed
to compile the widely used x/sys/uni
On Thu, 11 May 2023 at 17:04, Patrick Palka wrote:
> On Fri, 5 May 2023, Jonathan Wakely wrote:
>
> >
> >
> > On Fri, 5 May 2023 at 10:43, Florian Weimer wrote:
> > * Jonathan Wakely via Libstdc:
> >
> > > We could use strtod for a single-threaded target (i.e.
> > > !defined(_GL
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/24] arm: [MVE intrinsics] factorize vaddlvaq
>
> Factorize vaddlvaq
From: Ju-Zhe Zhong
1. Fix document description according Jeff && Richard.
2. Add LOOP_VINFO_USING_SELECT_VL_P for single rgroup.
3. Add LOOP_VINFO_USING_SLP_ADJUSTED_LEN_P for SLP multiple rgroup.
gcc/ChangeLog:
* doc/md.texi: Add seletc_vl pattern.
* internal-fn.def (SELECT_VL)
> On May 10, 2023, at 9:15 AM, Jan Hubicka wrote:
>
>> Honza,
>>> Main motivation for this was profiling programs that contain specific
>>> code paths for different CPUs (such as graphics library in Firefox or Linux
>>> kernel). In the situation training machine differs from the machine
>>> pro
On Thu, 11 May 2023 at 16:54, Thomas Rodgers wrote:
>
>
> On Thu, May 11, 2023 at 5:21 AM Mike Crowe via Libstdc++ <
> libstd...@gcc.gnu.org> wrote:
>
>> On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
>> > On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
>> > libs
On Fri, 5 May 2023, Jonathan Wakely wrote:
>
>
> On Fri, 5 May 2023 at 10:43, Florian Weimer wrote:
> * Jonathan Wakely via Libstdc:
>
> > We could use strtod for a single-threaded target (i.e.
> > !defined(_GLIBCXX_HAS_GTHREADS) by changing the global locale using
> > s
On Thu, May 11, 2023 at 5:21 AM Mike Crowe via Libstdc++ <
libstd...@gcc.gnu.org> wrote:
> On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
> > On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
> > libstd...@gcc.gnu.org> wrote:
> >
> > > This patch would avoid TSan fa
Pushed to wwwdocs (better late than never).
-- >8 --
---
htdocs/gcc-13/changes.html | 14 ++
1 file changed, 14 insertions(+)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index bd022ed2..39414e18 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/cha
From: Lili Cui
Add a param for the chain with FMA in reassoc pass to make it more friendly to
the fma pass later. First to detect if this chain has ability to
generate more than 2 FMAs,if yes and param_reassoc_max_chain_length_with_fma
is enabled, We will rearrange the ops so that they can be com
> -Original Message-
> From: Richard Biener
> Sent: Thursday, May 11, 2023 6:53 PM
> To: Cui, Lili
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 1/2] PR gcc/98350:Add a param to control the length of
> the chain with FMA in reassoc pass
Hi Richard,
Thanks for helping to review the
While I was looking at differences before and after
r14-569-g21e2ef2dc25de3, I noticed that one phi node was
not being removed.
For an example, while compiling combine.cc, in expand_field_assignment,
we would remove `# pos_51 = PHI `
but we don't any more since pos_51 has more than zero users
but i
> From: "Roger Sayle"
> Date: Tue, 2 May 2023 00:37:14 +0100
> Jeff Law wrote:
> > This patch converts the xstormy16 patch to LRA. It introduces a code
> > quality regression in the shiftsi testcase, but it also fixes numerous
> > aborts/errors. IMHO it's a good tradeoff.
>
> I've investigat
On 5/11/23 02:29, Robin Dapp via Gcc-patches wrote:
Hi,
this patch allows mklog.py to be called with a commit hash directly.
So, instead of
git show | git gcc-mklog
git gcc-mklog --commit
can be used.
When no is given but --commit is specified, HEAD is used
instead. The behavior w
We accept this testcase since r13-806-g221acd67ca50f8.
PR c++/103807
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ1.C: New test.
---
gcc/testsuite/g++.dg/cpp2a/lambda-targ1.C | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/cpp2a/
PR 109766 is an interesting case of large code being generated on x86_64,
caused by an interaction/conflict between register allocation and hardreg
cprop, that's tricky to fix/resolve within the middle-end.
The task/challenge is to push a DImode value in an SSE register on to
the stack, when opti
On 5/11/23 04:33, Robin Dapp wrote:
"csr_operand" does seem wrong, though, as that just accepts constants.
Maybe "arith_operand" is the way to go? I haven't looked at the
V immediates though.
I was pondering changing the shift-count operand to QImode everywhere
but that indeed does not help
LGTM, thanks :)
On Thu, May 11, 2023 at 8:47 PM Robin Dapp wrote:
>
> > OK, you can go ahead commit patch. I am gonna send another patch to
> > fix this.
> I agree that we should handle more constants but I'd still rather go
> ahead now and fix things later. The patch is more about the test
> ra
Sorry for disturbing, fixed my silly mistake in PATCH v6 and passed x86
regression test. If no more concern, will commit after pass the x86 regression
test.
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, May 11, 2023 6:56 PM
To: Richard Sandiford
Cc: gcc-patches@gcc.gnu.org; ju
From: Pan Li
The decl_or_value is defined as void * before this PATCH. It will take
care of both the tree_node and rtx_def. Unfortunately, given a void
pointer cannot tell the input is tree_node or rtx_def.
Then we have some implicit structure layout requirement similar as
below. Or we will touc
> OK, you can go ahead commit patch. I am gonna send another patch to
> fix this.
I agree that we should handle more constants but I'd still rather go
ahead now and fix things later. The patch is more about the test
rather than the actual change anyway.
Jeff already ack'ed v1, maybe waiting for K
"juzhe.zh...@rivai.ai" writes:
> Thanks. I have read rgroup descriptions again.
> Still I am not fully understand it clearly, bear with me :)
>
> I don't known how to differentiate Case 2 and Case 3.
>
> Case 2 is multiple rgroup for SLP.
> Case 3 is multiple rgroup for non-SLP (VEC_PACK_TRUNC)
>
On Thu, 11 May 2023 at 13:19, Mike Crowe wrote:
> On Wednesday 10 May 2023 at 12:31:12 +0100, Jonathan Wakely wrote:
> > On Wed, 10 May 2023 at 12:20, Jonathan Wakely via Libstdc++ <
> > libstd...@gcc.gnu.org> wrote:
> >
> > > This patch would avoid TSan false positives when using timed waiting
>
ChangeLog:
* MAINTAINERS: Sort.
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c380bef5c5..e4dee76e2df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -521,7 +521,6 @@ James Lemke
Ilya Le
From: Pan Li
The VMSET simplification RVV integer comparision has merged already.
This patch would like to update the comments for the cases that the
define_split will act on.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector.md: Add comments for simplifying to vmset.
Signed
Implement vmlaq, vmlasq, vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq
using the new MVE builtins framework.
2022-12-12 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaq, vmlasq, vqdmlahq)
(vqdmlashq, vqrdmlahq, vqrdmlashq): New.
* config/arm/arm-mv
Implement vmladavaq, vmladavaxq, vmlsdavaq, vmlsdavaxq using the new
MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm-mve-builtins-base.def (vmlad
Implement vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq using
the new MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins
Factorize vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq builtins so
that they use the same parameterized names.
2022-10-25 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P):
New.
(mve_insn): Add vmlaldava, vmlaldavax, vmlslda
Implement vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq using the
new MVE builtins framework.
2022-10-25 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm-mve-builtins-base.de
1 - 100 of 167 matches
Mail list logo
