From: Pan Li
This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:
vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin
PR106907 has few warnings spotted from cppcheck. In that addressing duplicate
expression issue here. Here the same expression is used twice in logical
AND(&&) operation which result in same result so removing that.
2023-06-05 Jeevitha Palanisamy
gcc/
PR target/106907
* config/r
On Mon, Jun 5, 2023 at 7:43 AM Andrew Pinski wrote:
>
> On Sun, Jun 4, 2023 at 10:24 PM Richard Biener via Gcc-patches
> wrote:
> >
> >
> >
> > > Am 05.06.2023 um 06:42 schrieb Andrew Pinski via Gcc-patches
> > > :
> > >
> > > On sh target, there is a MULTILIB_DIRNAMES (or is it MULTILIB_OPTION
On Sun, Jun 4, 2023 at 11:41 PM Jeff Law via Gcc-patches
wrote:
>
> While investigating a RISC-V backend patch from Jivan I noticed a
> regression in terms of dynamic instruction counts for the omnetpp
> benchmark in spec2017.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620577.html
>
>
juzhe.zh...@rivai.ai writes:
> + /* If we're using decrement IV approach in loop control, we can use output
> of
> + SELECT_VL to adjust IV of loop control and data reference when it
> satisfies
> + the following checks:
> +
> + (a) SELECT_VL is supported by the target.
> + (b) L
Hi Pat,
Thanks for fixing this and sorry for the late review!
on 2023/4/18 20:22, Pat Haugen wrote:
> Updated from prior patch to also disable for int128.
>
>
> Disable generation of scalar modulo instructions.
>
> It was recently discovered that the scalar modulo instructions can suffer
> not
On Fri, Jun 2, 2023 at 6:57 PM Jason Merrill via Gcc-patches
wrote:
>
> Since Jonathan approved the library change, I'm looking for middle-end
> approval for the tree-eh change, even without advice on the potential
> follow-up.
>
> On 5/24/23 14:55, Jason Merrill wrote:
> > Middle-end folks: any t
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-restore-cfi.c: New test to check save-restore
cfi directives.
---
.../gcc.target/riscv/save-restore-cfi.c | 17 +
1 file changed, 17 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/save-restore-cfi.
On Fri, Jun 2, 2023 at 11:54 AM SenthilKumar.Selvaraj--- via
Gcc-patches wrote:
>
> Hi,
>
> This patch fixes an ICE when an optimize attribute changes the prevailing
> optimization level.
>
> I found https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105069 describing the
> same ICE for the sh target, w
After expanding directly to rtl instead of
creating a tree, we could end up with
a const_int which is not ready to be handled
by extract_bit_field.
So need to the constant folding here instead.
OK? bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR middle-end/110117
gcc/
In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
turn off the bit tracking part of CCP so we would lose out
what TER was able to do before hand. This moves around the
TER code so that it is used instead of just the nonzerobits.
It also makes it easier to remove the TER part of the code
On Sun, Jun 4, 2023 at 10:24 PM Richard Biener via Gcc-patches
wrote:
>
>
>
> > Am 05.06.2023 um 06:42 schrieb Andrew Pinski via Gcc-patches
> > :
> >
> > On sh target, there is a MULTILIB_DIRNAMES (or is it MULTILIB_OPTIONS)
> > named m2,
> > this conflicts with the langauge m2. So when you do
on 2023/6/1 00:57, Ian Lance Taylor wrote:
> On Wed, May 31, 2023 at 12:41 AM Kewen.Lin via Gcc-patches
> wrote:
>>
libgcc/ChangeLog:
* config/i386/morestack.S: Use @init_array rather than
@progbits for section type of section .init_array.
* config/rs6000/mo
> Am 05.06.2023 um 06:42 schrieb Andrew Pinski via Gcc-patches
> :
>
> On sh target, there is a MULTILIB_DIRNAMES (or is it MULTILIB_OPTIONS) named
> m2,
> this conflicts with the langauge m2. So when you do a `make clean`, it will
> remove
> the m2 directory and then a build will fail. Now
On sh target, there is a MULTILIB_DIRNAMES (or is it MULTILIB_OPTIONS) named m2,
this conflicts with the langauge m2. So when you do a `make clean`, it will
remove
the m2 directory and then a build will fail. Now since r0-78222-gfa9585134f6f58,
the multilib directories are no longer created in the
From: Ju-Zhe Zhong
This patch address comments from Richard and rebase to trunk.
This patch is adding SELECT_VL middle-end support
allow target have target dependent optimization in case of
length calculation.
This patch is inspired by RVV ISA and LLVM:
https://reviews.llvm.org/D99750
The SELE
> +static bool
> +riscv_frame_pointer_required (void)
> +{
> + if (riscv_save_frame_pointer && !crtl->is_leaf)
> +return true;
> +
> + return false;
> +}
>
> Can be simplified to return riscv_save_frame_pointer && !crtl->is_leaf;
Nice. It's much simpler. Will modify in another patch.
> +
> On Thu, 1 Jun 2023, Andre Vieira (lists) wrote:
>
> > Hi,
> >
> > This is a follow-up of the internal function patch to add widening and
> > narrowing patterns. This patch improves the inliner cost estimation for
> > internal functions.
>
> I have no idea why calls are special in IPA analyze_
Hi Jeff,
Yes, there's a requirement to support backtrace based on the fp+ra.
And the unwind/cfa is not acceptable because it will add additional
sections to the binary. Currently, -fno-omit-frame-pointer can not
save the ra for the leaf function. So we need to add another option
like ARM/X86 to su
In 4fe6e12204535545edf7f035d4dc79c1404058cf, I should have added
Matthew Fortune to the Write After Approval section, while replacing
the MIPS Maintainer position.
ChangeLog:
* MAINTAINERS (Write After Approval): move Matthew Fortune
to Write After Approval.
---
MAINTAINERS | 1 +
This patch only support vec_pack/unpacks optabs for vector modes whose lenth >=
128.
For 32/64-bit vector, they're more hanlded by BB vectorizer with
truncmn2/extendmn2/fix{,uns}_truncmn2.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready to push to trunk.
gcc/ChangeLog:
*
Some nit comments.
+static bool
+riscv_frame_pointer_required (void)
+{
+ if (riscv_save_frame_pointer && !crtl->is_leaf)
+return true;
+
+ return false;
+}
Can be simplified to return riscv_save_frame_pointer && !crtl->is_leaf;
+ riscv_save_frame_pointer = false;
+ if (TARGET_OMIT_LEAF_
Committed, thanks Jeff.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Sunday, June 4, 2023 11:40 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [NFC] RISC-V: Reo
Committed, thanks Jeff.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Sunday, June 4, 2023 11:28 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: S
Hi, Richard. Thanks for the comments.
>> I think it would be worth saying in more detail why we only use SELECT_VL
>> for single rgroups. I assume the reason is to simplify the pointer IV
>> updates. Is that right?
Yes.
>> The difficulty is
>> that an rgroup that controls N vector loads (say)
Sorry for the slow review.
I don't know the IV-related parts well enough to review those properly,
but they looked reasonable to me. Hopefully Richi can comment.
I'm curious though. For:
> + tree step = vect_dr_behavior (vinfo, dr_info)->step;
> +
> + [...]
> + poly_uint64 bytesize = GET_MO
While investigating a RISC-V backend patch from Jivan I noticed a
regression in terms of dynamic instruction counts for the omnetpp
benchmark in spec2017.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620577.html
The code we we with Jivan's patch at expansion time looks like this for
ea
On Sun, Jun 4, 2023 at 12:45 AM Roger Sayle wrote:
>
>
> This patch is the latest revision of my patch to add support for the
> STC (set carry flag), CLC (clear carry flag) and CMC (complement
> carry flag) instructions to the i386 backend, incorporating Uros'
> previous feedback. The significant
With Vlad's recent LRA fix to the elimination code, the H8 can be
converted to LRA.
This patch has two changes of note.
First, this turns Zz into a standard constraint. This helps reloading
for the H8/SX movqi pattern.
Second, this drops the whole pattern for the SX bit memory operations.
Hi YunQiang/Maciej,
Given that I have simply been unable to fulfill any of the duties of
maintaining a port in GCC due to various other commitments, I am
thrilled that YunQiang has stepped up to take it on. I have no
objection to either being removed or left, as a rather silent partner,
but would
On Sat, Jun 3, 2023 at 3:52 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes both the boolean evaluation of and the branching of
> EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
> cation the ABS machine instruction on Xtensa returns INT_MIN iff INT_MIN,
> o
On 5/9/23 07:43, Jiufu Guo wrote:
Thanks for point out this! Yes, BLKmode rtx may not always be a MEM.
MEM_SIZE is only ok for MEM after the it's known size is computed.
Here MEM_SIZE is fine just because it is an stack rtx corresponding
to the type of parameter and returns which has been co
On 5/20/23 09:04, Andrew Pinski via Gcc-patches wrote:
This is a case which I noticed while working on the previous patch.
Sometimes we end up with `a == CST` instead of comparing against 0.
This happens in the following code:
```
unsigned f(unsigned t)
{
if (t & ~(1<<30)) __builtin_unreach
On 5/20/23 09:04, Andrew Pinski via Gcc-patches wrote:
While working something else, I noticed we could improve
the following function code generation:
```
unsigned f(unsigned t)
{
if (t & ~(1<<30)) __builtin_unreachable();
return t != 0;
}
```
Right know we just emit a comparison agains
On 6/4/23 03:11, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
This patch is just reorganizing the functions for the following patch.
I put rvv_builder and emit_* functions located before expand_const_vector
function since I will use them in expand_const_vector in the following patch.
gcc/
On 6/4/23 03:25, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
Since the following patch will calls expand_vec_perm with
splitted arguments, change the expand_vec_perm interface in
this patch.
gcc/ChangeLog:
* config/riscv/autovec.md: Split arguments.
* config/riscv/riscv
Committed, thanks Jeff.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Sunday, June 4, 2023 9:55 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Re
On 6/4/23 02:51, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
PR target/110109
This patch is to fix PR110109 issue. This issue happens is because:
(define_insn_and_split "*vlmul_extx2"
[(set (match_operand: 0 "register_operand" "=vr, ?&vr")
(subreg:
(match_o
Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Kito Cheng
Sent: Sunday, June 4, 2023 9:38 PM
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ;
kito.cheng ; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
LGTM too, thanks
On Sun, Jun 4, 2023 at
LGTM too, thanks
On Sun, Jun 4, 2023 at 3:36 PM 钟居哲 wrote:
>
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-04 15:19
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
> From: Pan Li
>
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Sunday, June 4, 2023 9:14 PM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com; pal...@rivosinc.com;
rdapp@gmail.com
Subject: Re: [NFC] RISC-V: M
Lgtm
於 2023年6月4日 週日，17:37寫道：
> From: Juzhe-Zhong
>
> Move all optimization patterns into autovec-opt.md to make organization
> easier maintain.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*not): Move to
> autovec-opt.md.
> (*n): Ditto.
> * config/riscv/autovec.m
Hi Suwa-san,
On Sat, Jun 3, 2023 at 2:55 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
From: Juzhe-Zhong
Move all optimization patterns into autovec-opt.md to make organization
easier maintain.
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*not): Move to
autovec-opt.md.
(*n): Ditto.
* config/riscv/autovec.md (*not): Ditto.
(*n): Ditto.
* c
From: Juzhe-Zhong
Since the following patch will calls expand_vec_perm with
splitted arguments, change the expand_vec_perm interface in
this patch.
gcc/ChangeLog:
* config/riscv/autovec.md: Split arguments.
* config/riscv/riscv-protos.h (expand_vec_perm): Ditto.
* config
From: Juzhe-Zhong
This patch is just reorganizing the functions for the following patch.
I put rvv_builder and emit_* functions located before expand_const_vector
function since I will use them in expand_const_vector in the following patch.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (cla
From: Juzhe-Zhong
PR target/110109
This patch is to fix PR110109 issue. This issue happens is because:
(define_insn_and_split "*vlmul_extx2"
[(set (match_operand: 0 "register_operand" "=vr, ?&vr")
(subreg:
(match_operand:VLMULEXT2 1 "register_operand" " 0, vr") 0))]
On Sat, Jun 3, 2023 at 7:31 PM Roger Sayle wrote:
>
>
> This patch fixes PR target/110083, an ICE-on-valid regression exposed by
> my recent PTEST improvements (to address PR target/109973). The latent
> bug (admittedly mine) is that the scalar-to-vector (STV) pass doesn't update
> or delete REG_
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-04 15:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
From: Pan Li
This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for b
From: Pan Li
This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for below instructions
vfwcvt.f.f.v
vfncvt.f.f.w
Then users can leverage the instrinsic APIs to perform the conversion
between RVV vector single float point and half float point.
Signed-off-by: Pan Li
g
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