Re: [PATCH V6] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs

>>>If the pattern is not allowed to fail, then what code enforces the bias >>>argument's restrictions?  I don't see it in the generic expander code. > > I have no ideal since this is just copied from len_load/len_store which is  > s390 target dependent stuff.  > > I have sent V7 patch with fixing

[PATCH v2] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

From: Pan Li The rvv widdening reduction has 3 different patterns for zve128+, zve64 and zve32. They take the same iterator with different attributions. However, we need the generated function code_for_reduc (code, mode1, mode2). The implementation of code_for_reduc may look like below. code_for

[PATCH] Remove -save-temps from tests using -flto

The following removes -save-temps that doesn't seem to have any good reason from tests that also run with -flto added. That can cause ltrans files to race with other multilibs tested and I'm frequently seeing linker complaints that the architecture doesn't match here. I'm not sure whether the .lt

Re: [PATCH ver 5] rs6000: Add builtins for IEEE 128-bit floating point values

Hi Carl, on 2023/6/17 01:57, Carl Love wrote: > Kewen, GCC maintainers: > > Version 5, Tested the patch on P9 BE per request. Fixed up test case > to get the correct expected values for BE and LE. Fixed typos. > Updated the doc/extend.texi to clarify the vector arguments. Changed > test file

Re: [PATCH v2] RISC-V: Fix VWEXTF iterator requirement

LGTM. Thanks. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-06-19 13:52 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; Li Xu Subject: [PATCH v2] RISC-V: Fix VWEXTF iterator requirement gcc/ChangeLog: * config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the Zve32f extensio

[PATCH v2] RISC-V: Fix VWEXTF iterator requirement

gcc/ChangeLog: * config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the Zve32f extension. --- gcc/config/riscv/vector-iterators.md | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-itera

Re: [PATCH ver 2] rs6000, fix vec_replace_unaligned builtin arguments

Hi Carl, on 2023/6/16 00:00, Carl Love wrote: > GCC maintainers: > > Version 2, fixed various typos. Updated the change log body to say the > instruction counts were updated. The instruction counts changed as a > result of changing the first argument of the vec_replace_unaligned > builtin call

Re: [PATCH] RISC-V: Fix iterator requirement

I understand this patch is fixing VWF, VWF_ZVE64, VWEXTF, base on current upstream codes. I agree with "VWEXTF" changes. But not "VWF" "VWF_ZVE64", since current reduction pattern has bugs on ZVE32* and ZVE64* and we have refactored them: https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622

Re: RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

I notice VWF_ZVE64 should be removed. juzhe.zh...@rivai.ai From: Li, Pan2 Date: 2023-06-19 09:29 To: 钟居哲; gcc-patches CC: rdapp.gcc; Jeff Law; Wang, Yanzhang; kito.cheng Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 Thanks Juzhe, will not send the V2 as only co

[PATCH] RISC-V: Fix iterator requirement

VWF is defined under TARGET_MIN_VLEN >= 128. VWEXTF: zvfh/zvfhmin depends on the Zve32f extension. gcc/ChangeLog: * config/riscv/vector-iterators.md: Fix requirement --- gcc/config/riscv/vector-iterators.md | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-)

Re: [PATCH 2/2] xtensa: constantsynth: Add new 2-insns synthesis pattern

On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa wrote: > > This patch adds a new 2-instructions constant synthesis pattern: > > - A non-negative square value that root can fit into a signed 12-bit: > => "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax" > > Due to the execution cost of t

Re: [PATCH 1/2] xtensa: Remove TARGET_MEMORY_MOVE_COST hook

On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa wrote: > > It used to always return a constant 4, which is same as the default > behavior, but doesn't take into account the effects of secondary > reloads. > > Therefore, the implementation of this target hook is removed. > > gcc/Chang

Re: [PATCH] rs6000, fix vec_replace_unaligned builtin arguments

Hi Carl, on 2023/6/16 00:00, Carl Love wrote: > On Tue, 2023-06-13 at 11:24 +0800, Kewen.Lin wrote: >> Hi Carl, >> >> on 2023/5/31 04:41, Carl Love wrote: >>> GCC maintainers: >>> >>> The following patch fixes the first argument in the builtin >>> definition >>> and the corresponding test cases.

Re: ping^^: [PATCH] rs6000: Enable const_anchor for 'addi'

Hi! David Edelsohn writes: > This Message Is From an External Sender > This message came from outside your organization. > > On Tue, May 30, 2023 at 11:00 PM Jiufu Guo wrote: > > Gentle ping... > > Jiufu Guo via Gcc-patches writes: > > > Gentle ping... > > > > Jiufu Guo via Gcc-patc

Re: [PATCH] Check SCALAR_INT_MODE_P in try_const_anchors

Hi, Richard Biener writes: > On Fri, 16 Jun 2023, Jiufu Guo wrote: > >> Hi, >> >> The const_anchor in cse.cc supports integer constants only. >> There is a "gcc_assert (SCALAR_INT_MODE_P (mode))" in >> try_const_anchors. >> >> In the latest code, some non-integer modes are used with const in

RE: [PATCH v2] x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F

> -Original Message- > From: Jan Beulich > Sent: Friday, June 16, 2023 2:22 PM > To: gcc-patches@gcc.gnu.org > Cc: Kirill Yukhin ; Liu, Hongtao > > Subject: [PATCH v2] x86: make VPTERNLOG* usable on less than 512-bit > operands with just AVX512F > > There's no reason to constrain this

RE: [PATCH v2] x86: correct and improve "*vec_dupv2di"

> -Original Message- > From: Jan Beulich > Sent: Friday, June 16, 2023 2:20 PM > To: gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao ; Kirill Yukhin > > Subject: [PATCH v2] x86: correct and improve "*vec_dupv2di" > > The input constraint for the %vmovddup alternative was wrong, as the upper

RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

Thanks Juzhe, will not send the V2 as only commit log change. Pan From: 钟居哲 Sent: Monday, June 19, 2023 6:02 AM To: Li, Pan2 ; gcc-patches Cc: rdapp.gcc ; Jeff Law ; Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 Add tar

[PATCH, rs6000] Generate mfvsrwz for all platforms and remove redundant zero extend [PR106769]

Hi, This patch modifies vsx extract expander and generates mfvsrwz/stxsiwx for all platforms when the mode is V4SI and the index of extracted element is 1 for BE and 2 for LE. Also this patch adds a insn pattern for mfvsrwz which can help eliminate redundant zero extend. Bootstrapped and teste

Re: [PATCH V3 1/4] rs6000: build constant via li;rotldi

Hi! Segher Boessenkool writes: > Hi! > > On Fri, Jun 16, 2023 at 04:34:12PM +0800, Jiufu Guo wrote: >> +/* Check if value C can be built by 2 instructions: one is 'li', another is >> + rotldi. >> + >> + If so, *SHIFT is set to the shift operand of rotldi(rldicl), and *MASK >> + is set to

[PATCH] RISC-V: Add VLS modes for GNU vectors

This patch is a propsal patch is **NOT** ready to push since after this patch the total machine modes will exceed 255 which will create ICE in LTO: internal compiler error: in bp_pack_int_in_range, at data-streamer.h:290 The reason we need to add VLS modes for following reason: 1. Enhance GNU ve

Re: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

Add target into changelog: PR target/110299 Otherwise, LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-18 23:13 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 From: Pa

Re: Extend fnsummary to predict SRA oppurtunities

Hi, as noticed by Jeff, this patch also triggers warning in one of LTO testcases. The testcase is reduced and warning seems legit, triggered by extra inlining. So I have just silenced it. Honza gcc/testsuite/ChangeLog: * gcc.dg/lto/20091013-1_0.c: Disable stringop-overread warning. di

Extend fnsummary to predict SRA oppurtunities

Hi, this patch extends ipa-fnsummary to anticipate statements that will be removed by SRA. This is done by looking for calls passing addresses of automatic variables. In function body we look for dereferences from pointers of such variables and mark them with new not_sra_candidate condition. Thi

[COMMITTED] RTL: Change return type of predicate and callback functions from int to bool

gcc/ChangeLog: * rtl.h (*rtx_equal_p_callback_function): Change return type from int to bool. (rtx_equal_p): Ditto. (*hash_rtx_callback_function): Ditto. * rtl.cc (rtx_equal_p): Change return type from int to bool and adjust function body accordingly. * early-remat.cc (

Re: [pushed] c/c++: use positive tone in missing header notes [PR84890]

David Malcolm via Gcc-patches writes: > Quoting "How a computer should talk to people" (as quoted > in "Concepts Error Messages for Humans"): > > "Various negative tones or actions are unfriendly: being manipulative, > not giving a second chance, talking down, using fashionable slang, > blaming. W

[libstdc++] Improve M_check_len

Hi, _M_check_len is used in vector reallocations. It computes __n + __s but does checking for case that (__n + __s) * sizeof (Tp) would overflow ptrdiff_t. Since we know that __s is a size of already allocated memory block if __n is not too large, this will never happen on 64bit systems since memor

Re: [PATCH 0/2] RISC-V: New pass to optimize calculation of offsets for memory operations.

On 6/15/23 09:30, Manolis Tsamis wrote: Thanks for reporting. I also noticed this while reworking the implementation for v2 and I have fixed it among other things. Sounds good. I stumbled across another problem while testing V2. GEN_INT can create a non-canonical integer constant (and on

[committed] Fix arc assumption that insns are not re-recognized

Testing the V2 version of Manolis's fold-mem-offsets patch exposed a minor bug in the arc backend. The movsf_insn pattern has constraints which allow storing certain constants to memory. reload/lra will target those alternatives under the right circumstances. However the insn's condition req

Optimize std::max early

Hi, we currently produce very bad code on loops using std::vector as a stack, since we fail to inline push_back which in turn prevents SRA and we fail to optimize out some store-to-load pairs (PR109849). I looked into why this function is not inlined and it is inlined by clang. We currently estim

[PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

From: Pan Li The rvv widdening reduction has 3 different patterns for zve128+, zve64 and zve32. They take the same iterator with different attributions. However, we need the generated function code_for_reduc (code, mode1, mode2). The implementation of code_for_reduc may look like below. code_for

[RFC] Workaround LRA reload issue with SUBREGs in SET_DEST.

I was wondering whether I could ask a LRA/reload expert for their help with a better fix with this issue. For the testcase (from sse2-v1ti-mov-1.c): typedef unsigned __int128 uv1ti __attribute__ ((__vector_size__ (16))); uv1ti foo(__int128 x) { return (uv1ti)x; } we currently generate (with -O2

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

Thanks for cleaning up codes for future's ABI support patch. Let's wait for Jeff or Robin comments. Thanks. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-06-18 19:41 To: gcc-patches CC: juzhe.zhong; yanzhang.wang; kito.cheng; palmer; jeffreyalaw Subject: [PATCH] RISC-V: Add tuple vector mod

Re: [PATCH v2] RISC-V: Bugfix for RVV float reduction in ZVE32/64

Thanks for fixing it for me. LGTM now. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-18 10:57 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v2] RISC-V: Bugfix for RVV float reduction in ZVE32/64 From: Pan Li The rvv integer re

Re: [pushed][PATCH v3] LoongArch: Avoid non-returning indirect jumps through $ra [PR110136]

Hi, On 6/15/23 17:03, Xi Ruoyao wrote: Xuerui: I guess this makes it sensible to show "ret" instead of "jirl $zero, $ra, 0" in objdump -d output, but I don't know how to implement it. Do you have some idea? Thanks for the suggestion! Actually I have previously made this patch series [1] whic

[PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

Hi, This patch does several things: 1. Adds the missed checking of tuple vector mode 2. Extend the scope of checking to all vector types, previously it was only for scalable vector types. 3. Simplify the logic of determining code of vector type which will lower to vector tmode cod

Re: [x86 PATCH] Add alternate representation for {and, or, xor}b %ah, %dh.

On Sun, Jun 18, 2023 at 11:35 AM Roger Sayle wrote: > > > A patch that I'm working on to improve RTL simplifications in the > middle-end results in the regression of pr78904-1b.c, due to changes in > the canonical representation of high-byte (%ah, %bh, %ch, %dh) logic. > This patch avoids/prevents

Re: [x86 PATCH] Refactor new ix86_expand_carry to set the carry flag.

On Sun, Jun 18, 2023 at 1:10 PM Roger Sayle wrote: > > > This patch refactors the three places in the i386.md backend that we > set the carry flag into a new ix86_expand_carry helper function, that > allows Jakub's recently added uaddc5 and usubc5 expanders > to take advantage of the recently adde

Re: [x86 PATCH] Standardize shift amount constants as QImode.

On Sun, Jun 18, 2023 at 11:05 AM Roger Sayle wrote: > > > This clean-up improves consistency within i386.md by using QImode for > the constant shift count in patterns that specify a mode. > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and w

[x86 PATCH] Refactor new ix86_expand_carry to set the carry flag.

This patch refactors the three places in the i386.md backend that we set the carry flag into a new ix86_expand_carry helper function, that allows Jakub's recently added uaddc5 and usubc5 expanders to take advantage of the recently added support for the stc instruction. This patch has been tested

[PATCH] Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg.

An x86 backend improvement that I'm working results in combine attempting to recognize: (set (reg:DI 87 [ xD.2846 ]) (ior:DI (subreg:DI (ashift:TI (zero_extend:TI (reg:DI 92)) (const_int 64 [0x40])) 0) (reg:DI 91))) where the lowpart SUBREG ha

[x86 PATCH] Add alternate representation for {and,or,xor}b %ah,%dh.

A patch that I'm working on to improve RTL simplifications in the middle-end results in the regression of pr78904-1b.c, due to changes in the canonical representation of high-byte (%ah, %bh, %ch, %dh) logic. This patch avoids/prevents those failures by adding support for the alternate representati

[x86 PATCH] Standardize shift amount constants as QImode.

This clean-up improves consistency within i386.md by using QImode for the constant shift count in patterns that specify a mode. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for ma

[PATCH 1/2] xtensa: Remove TARGET_MEMORY_MOVE_COST hook

It used to always return a constant 4, which is same as the default behavior, but doesn't take into account the effects of secondary reloads. Therefore, the implementation of this target hook is removed. gcc/ChangeLog: * config/xtensa/xtensa.cc (TARGET_MEMORY_MOVE_COST, xtensa_me

[PATCH 2/2] xtensa: constantsynth: Add new 2-insns synthesis pattern

This patch adds a new 2-instructions constant synthesis pattern: - A non-negative square value that root can fit into a signed 12-bit: => "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax" Due to the execution cost of the integer multiply instruction (MULL), this synthesis works only when the 32-bit