Re: [PATCH] RISC-V: Support strided load/store

Hi Juzhe, The pre-commit CI is seeing these new failures after applying this patch [1]: |FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_strided_load-1.c scan-tree-dump-times optimized " .MASK_LEN_STRIDED_LOAD" 132 FAIL:

[PATCH] RISC-V: Use riscv_subword_address for atomic_test_and_set

Other subword atomic patterns use riscv_subword_address to calculate the aligned address, shift amount, mask and !mask. atomic_test_and_set was implemented before the common function was added. After this patch all subword atomic patterns use riscv_subword_address. gcc/ChangeLog: *

[Commit Pending V2] RISC-V: Support strided load/store

This patch is depending on middle-end patches which are under review. I will commit it after middle-end patches are approved. Consider this following case: void foo (int * __restrict a, int * __restrict b, int stride, int n) { for (int i = 0; i < n; i++) a[i*stride] = b[i*stride] +

Re: [PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

On 10/31/23 17:51, Jeff Law wrote: We also have a non-orthogonality in the ABI sign extension rules between SI and DI, a few of us were talking about it on the internal slack (though the specifics were for a different patch, Vineet has a few in flight). So the old issue I was thinking

Re: [PATCH 0/4] Fix no-evex512 function attribute

On Tue, Oct 31, 2023 at 2:39 PM Haochen Jiang wrote: > > Hi all, > > These four patches are going to fix no-evex512 function attribute. The detail > of the issue comes following: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111889 > > My proposal for this problem is to also push "no-evex512"

Re: [PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

On 10/31/23 17:41, Palmer Dabbelt wrote: On Tue, 31 Oct 2023 16:18:35 PDT (-0700), jeffreya...@gmail.com wrote: On 10/31/23 12:35, Vineet Gupta wrote: riscv_promote_function_mode doesn't promote a SI to DI for libcalls case. The fix is what generic promote_mode () in explow.cc does. I

[Committed] NFC: Fix whitespace

Notice there is a whitspace issue in previous commit: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f66b2fc122b8a17591afbb881d580b32e8ddb708 Sorry for missing fixing this whitespace. Committed as it is obvious. gcc/ChangeLog: * tree-vect-slp.cc (vect_build_slp_tree_1): Fix whitespace.

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/31/23 18:05, Vineet Gupta wrote: On 10/30/23 13:33, Jeff Law wrote: +/* Helper function for riscv_extend_comparands to Sign-extend the OP. +   However if the OP is SI subreg promoted with an inner DI, such as +   (subreg/s/v:SI (reg/v:DI) 0 +   just peel off the SUBREG to get DI,

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/30/23 13:33, Jeff Law wrote: +/* Helper function for riscv_extend_comparands to Sign-extend the OP. +   However if the OP is SI subreg promoted with an inner DI, such as +   (subreg/s/v:SI (reg/v:DI) 0 +   just peel off the SUBREG to get DI, avoiding extraneous extension.  */ +

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/30/23 16:21, Vineet Gupta wrote: I don't guess you have data on how this impacts dynamic instruction counts on anything significant do you? No, haven't run it yet. I can fire one though. I doubt if this is as significant as the prev one, even if this is the right thing to do. Very

Re: [PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

On Tue, 31 Oct 2023 16:18:35 PDT (-0700), jeffreya...@gmail.com wrote: On 10/31/23 12:35, Vineet Gupta wrote: riscv_promote_function_mode doesn't promote a SI to DI for libcalls case. The fix is what generic promote_mode () in explow.cc does. I really don't understand why the old code didn't

RE: [PATCH v4] VECT: Refine the type size restriction of call vectorizer

The below test are passed for this patch. * The x86 bootstrap and regression test. * The aarch64 regression test. * The risc-v regression tests. * Ensure the lrintf standard name in RVV. Pan -Original Message- From: Li, Pan2 Sent: Tuesday, October 31, 2023 11:10 PM To:

[PATCH v2] RISC-V: Enable ztso tests on rv32

This patch transitions the ztso testcases to use the testsuite infrastructure, enabling the tests on both rv64 and rv32 targets. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to dg-options for dg-do compile. *

Re: [PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

On 10/31/23 12:35, Vineet Gupta wrote: riscv_promote_function_mode doesn't promote a SI to DI for libcalls case. The fix is what generic promote_mode () in explow.cc does. I really don't understand why the old code didn't work, but stepping thru the debugger shows old code didn't and fixed

[RFC] Make genautomata.cc output reflect insn-attr.h expectation:

genattr.cc currently generates insn-attr.h with the following structure: #if CPU_UNITS_QUERY extern int get_cpu_unit_code (const char *); extern int cpu_unit_reservation_p (state_t, int); #endif extern bool insn_has_dfa_reservation_p (rtx_insn *); however genautomata.cc generates

Re: [PING] [C PATCH, v2] Add Walloc-size to warn about insufficient size in allocations [PR71219]

On Tue, 31 Oct 2023, Martin Uecker wrote: > > + if (TREE_CODE (arg) == INTEGER_CST > > + && tree_int_cst_lt (arg, TYPE_SIZE_UNIT (ttl))) What if TYPE_SIZE_UNIT (ttl) is not an INTEGER_CST? I don't see any tests of the case of assigning to a pointer to a variably sized type.

Re: RFC: the proposal to resolve the missing dependency issue for counted_by attribute

On Tue, 31 Oct 2023, Qing Zhao wrote: > 2.3 A new semantic requirement in the user documentation of "counted_by" > > For the following structure including a FAM with a counted_by attribute: > > struct A > { >size_t size; >char buf[] __attribute__((counted_by(size))); > }; > > for

Re: [PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar reduction.

>> +int >> +internal_fn_else_index (internal_fn fn) > > The function needs a comment, maybe: > > /* If FN is an IFN_COND_* or IFN_COND_LEN_* function, return the index of the >argument that is used when the condition is false. Return -1 otherwise. > */ > > OK for the internal-fn* and

[pushed] analyzer: move class record_layout to its own .h/.cc

No functional change intended. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-5050-g37e1634ef1a6f1. gcc/ChangeLog: * Makefile.in (ANALYZER_OBJS): Add analyzer/record-layout.o. gcc/analyzer/ChangeLog: * record-layout.cc: New file, based on

[pushed] libcpp: eliminate MACRO_MAP_EXPANSION_POINT_LOCATION

This patch eliminates the function "MACRO_MAP_EXPANSION_POINT_LOCATION" (which hasn't been a macro since r6-739-g0501dbd932a7e9) in favor of a new line_map_macro::get_expansion_point_location accessor. No functional change intended. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.

[pushed] opts.cc: fix comment about DOCUMENTATION_ROOT_URL

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-5048-g8b4ac021cd1f63. gcc/ChangeLog: * opts.cc (get_option_url): Update comment; the requirement to pass DOCUMENTATION_ROOT_URL's value via -D was removed in r10-8065-ge33a1eae25b8a8. ---

[pushed] pretty-print: gracefully handle null URLs

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r14-5047-gb9e2088d297744. gcc/ChangeLog: * pretty-print.cc (pretty_printer::pretty_printer): Initialize m_skipping_null_url. (pp_begin_url): Handle URL being null. (pp_end_url):

Re: [PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar reduction.

Robin Dapp writes: > Changed as suggested. The difference to v5 is thus: > > + if (cond_fn_p) > + { > + gcall *call = dyn_cast (use_stmt); > + unsigned else_pos > + = internal_fn_else_index (internal_fn (op.code)); > + > + for (unsigned int

Re: [PATCH] RISC-V: Support strided load/store

Hi Juzhe, LGTM once the middle-end parts are in. Just tiny nits. Nothing that would warrant a V2, though. > +;; = > +;; == Stried Load/Store missing a 'd' here. > +(define_predicate "vector_stride_extension_operand" > +

[PATCH] Reduce false positives for -Wnonnull for VLA parameters [PR98541]

This is a revised part of previously posted patch which I split up. C FE changes which another false positive were already merged, but I still need approval for this middle-end change. It would be nice to get this in, because it fixes some rather annoying (for me atleast) false positive

Re: [PATCH v5] bpf: Improvements in CO-RE builtins implementation.

> On 10/31/23 09:58, David Faust wrote: >> Hi Cupertino, >> >> On 10/30/23 12:39, Cupertino Miranda wrote: >>> >>> Hi everyone, >>> >>> Please find a new version for the review as inline attachment. >>> >>> Best regards, >>> Cupertino >>> >> >> This version LGTM. >> Thanks! > > OK for trunk.

[PING] [C PATCH, v2] Add Walloc-size to warn about insufficient size in allocations [PR71219]

Am Montag, dem 18.09.2023 um 23:26 +0200 schrieb Martin Uecker: > > Compared to the previous version I changed the name of the > warning to "Walloc-size" which matches "Wanalyzer-allocation-size" > but is still in line with the other -Walloc-something warnings > we have. I also added it to

Re: RFC: the proposal to resolve the missing dependency issue for counted_by attribute

> On Oct 31, 2023, at 1:35 PM, Siddhesh Poyarekar wrote: > > On 2023-10-31 12:26, Qing Zhao wrote: >> Hi, >> I wrote a summary based on our extensive discussion, hopefully this can be >> served as an informal proposal. >> Please take a look at it and let me know any comment or suggestion. >>

[PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

riscv_promote_function_mode doesn't promote a SI to DI for libcalls case. The fix is what generic promote_mode () in explow.cc does. I really don't understand why the old code didn't work, but stepping thru the debugger shows old code didn't and fixed does. This showed up when testing Ajit's REE

__hardcfr_check_fail and BPF

Hi Alex. As you may know, in BPF we have to live (for now) with the constant pain from being limited to functions whose arguments can be compiled to get their arguments in five or less registers. The recently introduced __hardcfr_check_fail in the run-time component of hardcfr breaks the

[PATCH] c++: constantness of local var in constexpr fn [PR111703, PR112269]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Does it look OK for release branches as well for sake of PR111703? -- >8 -- potential_constant_expression was incorrectly treating most local variables from a constexpr function as (potentially) constant because it

RE: [PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

> Hi Michael, > >> The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp >> instead of strverscmp to check the mcpu version against feature >> options. By simply changing the define to use strverscmp, the new >> version 10.0 is treated correctly as a higher version than previous >>

Re: [PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

On 10/31/23 09:41, Frager, Neal wrote: Hi Michael, The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher

Re: [PATCH v5] bpf: Improvements in CO-RE builtins implementation.

On 10/31/23 09:58, David Faust wrote: > Hi Cupertino, > > On 10/30/23 12:39, Cupertino Miranda wrote: >> >> Hi everyone, >> >> Please find a new version for the review as inline attachment. >> >> Best regards, >> Cupertino >> > > This version LGTM. > Thanks! OK for trunk. Thanks. > >> >>

Re: [PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

On 10/31/23 09:41, Frager, Neal wrote: Hi Michael, The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher

Re: RFC: the proposal to resolve the missing dependency issue for counted_by attribute

On 2023-10-31 12:26, Qing Zhao wrote: Hi, I wrote a summary based on our extensive discussion, hopefully this can be served as an informal proposal. Please take a look at it and let me know any comment or suggestion. There are some (???) in the section 3.2 and 3.6, those are my questions

Re: [PATCH] rs6000, Add missing overloaded bcd builtin tests

Segher: On Tue, 2023-10-31 at 11:17 -0500, Segher Boessenkool wrote: > > You could use gcov to see which rs6000 builtins are not exercised by > anything in the testsuite, maybe. This probably can be automated > pretty > nicely. I will take a look at gcov. I just did some relatively simple

[Committed 2/2] RISC-V: Require a extension for testcases with atomic insns

On 10/31/23 06:07, Jeff Law wrote: On 10/30/23 18:49, Patrick O'Neill wrote: Add testsuite infrastructure for the A extension and use it to require the A extension for dg-do run and add the add extension for non-A dg-do compile. gcc/testsuite/ChangeLog: *

[Committed 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores

On 10/31/23 06:05, Jeff Law wrote: On 10/30/23 18:49, Patrick O'Neill wrote: Non-atomic targets are currently prevented from using the optimized fencing for seq_cst load/seq_cst store. This patch removes that constraint. gcc/ChangeLog: * config/riscv/sync-rvwmo.md

[committed 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension

From: Christoph Müllner The XTheadMemIdx ISA extension provides a additional load and store instructions with new addressing modes. The following memory accesses types are supported: * load: b,bu,h,hu,w,wu,d * store: b,h,w,d The following addressing modes are supported: * immediate offset with

[committed 2/2] riscv: thead: Add support for the XTheadFMemIdx ISA extension

From: Christoph Müllner The XTheadFMemIdx ISA extension provides additional load and store instructions for floating-point registers with new addressing modes. The following memory accesses types are supported: * load/store: [w,d] (single-precision FP, double-precision FP) The following

Re: [PATCH v5] bpf: Improvements in CO-RE builtins implementation.

Hi Cupertino, On 10/30/23 12:39, Cupertino Miranda wrote: > > Hi everyone, > > Please find a new version for the review as inline attachment. > > Best regards, > Cupertino > This version LGTM. Thanks! > > Changes from v4: > - Implemented TARGET_DELEGITIMIZE_ADDRESS target hook as the

RE: [PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

Hi Michael, > The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp > instead of strverscmp to check the mcpu version against feature > options. By simply changing the define to use strverscmp, the new > version 10.0 is treated correctly as a higher version than previous >

Re: [Patch, fortran] PR64120

On Tue, Oct 31, 2023 at 02:11:08PM +, Paul Richard Thomas wrote: > I found this 'obvious' fix, while going through PRs assigned to me. > > Regtests. OK for mainline? > Yes. Fell free to backport if you have time and desire. -- Steve

Re: [PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

On 10/30/23 10:02, Neal Frager wrote: The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than

RFC: the proposal to resolve the missing dependency issue for counted_by attribute

Hi, I wrote a summary based on our extensive discussion, hopefully this can be served as an informal proposal. Please take a look at it and let me know any comment or suggestion. There are some (???) in the section 3.2 and 3.6, those are my questions seeking for help. -:) Thanks again for

Re: [PATCH] rs6000, Add missing overloaded bcd builtin tests

On Tue, Oct 31, 2023 at 08:31:25AM -0700, Carl Love wrote: > > I just found that actually they have the test coverage, because we > > have > > > > #define __builtin_bcdcmpeq(a,b) __builtin_vec_bcdsub_eq(a,b,0) > > #define __builtin_bcdcmpgt(a,b) __builtin_vec_bcdsub_gt(a,b,0) > > #define

[pushed][PR111917][RA]: Fixing LRA cycling for multi-reg variable containing a fixed reg

The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111971 Successfully bootstrapped and tested on x86-64, aarch64, pp64le. commit df111406b4ea1fe2890e94d51655e571cf260d29 Author: Vladimir N. Makarov Date: Tue Oct 31 10:54:43 2023 -0400 [RA]: Fixing LRA cycling for

Re: [PATCH] rs6000, Add missing overloaded bcd builtin tests

On Tue, 2023-10-31 at 10:34 +0800, Kewen.Lin wrote: > Hi Carl, > > on 2023/10/31 08:08, Carl Love wrote: > > GCC maintainers: > > > > The following patch adds tests for two of the rs6000 overloaded > > built- > > ins that do not have tests. Additionally the GCC documentation > > file > > I

[PATCH v4] VECT: Refine the type size restriction of call vectorizer

From: Pan Li Update in v4: * Append the check to vectorizable_internal_function. Update in v3: * Add func to predicate type size is legal or not for vectorizer call. Update in v2: * Fix one ICE of type assertion. * Adjust some test cases for aarch64 sve and riscv vector. Original log: The

[Patch, fortran] PR64120

I found this 'obvious' fix, while going through PRs assigned to me. Regtests. OK for mainline? Cheers Paul Fortran: Allocatable automatic charlen must not be saved [PR64120]. 2023-10-31 Paul Thomas gcc/fortran PR fortran/64120 * trans-decl.cc (gfc_trans_deferred_vars): Detect automatic

RE: [PATCH v3] VECT: Refine the type size restriction of call vectorizer

> can you instead amend vectorizable_internal_function to contain the check, > returning IFN_LAST if it doesn't hold? Sure, will send v4 for this. Pan -Original Message- From: Richard Biener Sent: Tuesday, October 31, 2023 8:58 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org;

RE: [PATCH] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize

Passed the x86 bootstrap and regression tests. Pan -Original Message- From: Juzhe-Zhong Sent: Tuesday, October 31, 2023 6:08 PM To: gcc-patches@gcc.gnu.org Cc: richard.sandif...@arm.com; rguent...@suse.de; jeffreya...@gmail.com; Juzhe-Zhong Subject: [PATCH] VECT: Support

RE: [PATCH V2] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN

Passed the x86 bootstrap and regression tests. Pan -Original Message- From: Juzhe-Zhong Sent: Tuesday, October 31, 2023 5:59 PM To: gcc-patches@gcc.gnu.org Cc: rguent...@suse.de; jeffreya...@gmail.com; richard.sandif...@arm.com; rdapp@gmail.com; Juzhe-Zhong Subject: [PATCH V2]

Re: [PATCH, OpenACC 2.7] Adjust acc_map_data/acc_unmap_data interaction with reference counters

Hi Chung-Lin! On 2023-06-22T18:03:37+0800, Chung-Lin Tang via Gcc-patches wrote: > This patch adjusts the implementation of acc_map_data/acc_unmap_data API > library > routines to more fit the description in the OpenACC 2.7 specification. Thanks! > Instead of using REFCOUNT_INFINITY, we now

Add OpenACC 'acc_map_data' variant to 'libgomp.oacc-c-c++-common/deep-copy-8.c' (was: [PATCH 11/13] OpenACC 2.6 deep copy: C and C++ execution tests)

Hi! On 2019-12-17T22:04:54-0800, Julian Brown wrote: > This patch has been broken out of the "OpenACC 2.6 manual deep copy > support" patch, [...] > This part adds C and C++ execution tests to libgomp. Pushed to master branch commit 3e888f94624294d2b9b34ebfee0916768e5d9c3f "Add OpenACC

Re: [PATCH v4] [tree-optimization/110279] Consider FMA in get_reassociation_width

On Sun, Oct 8, 2023 at 6:40 PM Di Zhao OS wrote: > > Attached is a new version of the patch. > > > -Original Message- > > From: Richard Biener > > Sent: Friday, October 6, 2023 5:33 PM > > To: Di Zhao OS > > Cc: gcc-patches@gcc.gnu.org > > Subject: Re: [PATCH v4]

Re: [PATCH v2 2/2] riscv: thead: Add support for the XTheadFMemIdx ISA extension

On Sun, Oct 29, 2023 at 11:25 PM Jeff Law wrote: > > > > On 10/20/23 03:53, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The XTheadFMemIdx ISA extension provides additional load and store > > instructions for floating-point registers with new addressing modes. > > > > The

Re: [PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension

On Sun, Oct 29, 2023 at 10:44 PM Jeff Law wrote: > > > > On 10/20/23 03:53, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The XTheadMemIdx ISA extension provides a additional load and store > > instructions with new addressing modes. > > > > The following memory accesses types

[OG13][committed] OpenMP/Fortran: Fix parsing of metadirectives with BLOCK

This is an OG13-only patch as metadirectives are not yet on mainline. I think it is a side effect of the backported my mainline patch that fixed strictly-nested blocks that was backported to OG13 on Oct 8, 2023 in OG13 commit 36e5f02e64bd4b5b1eaf89993a63c56b01cd4e7c. Tobias -

Re: [PATCH 2/2] tree-optimization/111131 - SLP for non-IFN gathers

On Tue, 31 Oct 2023, Thomas Schwinge wrote: > Hi! > > On 2023-10-19T11:47:14+, Richard Biener wrote: > > The following implements SLP vectorization support for gathers > > without relying on IFNs being pattern detected (and supported by > > the target). That includes support for emulated

Re: [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns

On 10/30/23 18:49, Patrick O'Neill wrote: Add testsuite infrastructure for the A extension and use it to require the A extension for dg-do run and add the add extension for non-A dg-do compile. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension

Re: [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores

On 10/30/23 18:49, Patrick O'Neill wrote: Non-atomic targets are currently prevented from using the optimized fencing for seq_cst load/seq_cst store. This patch removes that constraint. gcc/ChangeLog: * config/riscv/sync-rvwmo.md (atomic_load_rvwmo): Remove TARGET_ATOMIC

Re: [PATCH] RISC-V: Enable ztso tests on rv32

On 10/30/23 18:47, Patrick O'Neill wrote: This patch transitions the ztso testcases to use the testsuite infrastructure, enabling the tests on both rv64 and rv32 targets. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to

Re: [PATCH v3] VECT: Refine the type size restriction of call vectorizer

On Mon, Oct 30, 2023 at 1:23 PM wrote: > > From: Pan Li > > Update in v3: > > * Add func to predicate type size is legal or not for vectorizer call. > > Update in v2: > > * Fix one ICE of type assertion. > * Adjust some test cases for aarch64 sve and riscv vector. > > Original log: > > The

Re: hardcfr: support checking at abnormal edges [PR111943]

[adding list] On Oct 27, 2023, rep.dot@gmail.com wrote: > + from E and FALES from other preds, split the whole block, add a > s/FALES/FALSE/ Thanks, I've just installed the patch including the typo fix. -- Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/

Re: [PATCH] VECT: Support SLP MASK_LEN_GATHER_LOAD with conditional mask

On Thu, 26 Oct 2023, Juzhe-Zhong wrote: > This patch leverage current MASK_GATHER_LOAD to support SLP > MASK_LEN_GATHER_LOAD with condtional mask. > > Unconditional MASK_LEN_GATHER_LOAD (base, offset, scale, zero, -1) SLP is not > included in this patch > since it seems that we can't support

RE: Re: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

Thanks xuli for enabling this feature, we can update the CI of rvv-intrinsic-doc for overloaded API(s) after committed. Pan -Original Message- From: Li Xu Sent: Tuesday, October 31, 2023 7:37 PM To: juzhe.zh...@rivai.ai Cc: gcc-patches ; kito.cheng ; palmer Subject: Re: Re: [PATCH

[PATCH] tree-optimization/112305 - SCEV cprop and conditional undefined overflow

The following adjusts final value replacement to also rewrite the replacement to defined overflow behavior if there's conditionally evaluated stmts (with possibly undefined overflow), not only when we "folded casts". The patch hooks into expression_expensive for this. Bootstrapped and tested on

Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.

Thanks, going to commit the attached. Regards Robin This patch adds expanders for fmin and fmax. As per RISC-V V Spec 1.0 vfmin/vfmax are IEEE 754-2019 compliant which differs from IEEE 754-2008 that fmin/fmax require (particularly in the signaling-NaN handling). Therefore the pattern

Re: [PATCH v2] swap: Fix incorrect lane extraction by vec_extract() [PR106770]

Hi Segher, My replies are inlined: On 29/10/23 10:16 am, Segher Boessenkool wrote: > Hi! > > Please say "rs6000/p8swap:" in the subject, not "swap:" :-) > > On Sun, Sep 10, 2023 at 10:58:32PM +0530, Surya Kumari Jangala wrote: >> Another issue with always handling swappable instructions is that

Re: Re: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

All overload and non-overload intrinsics have been tested successfully on gcc and g++. Thanks. > -原始邮件-发件人:"juzhe.zh...@rivai.ai" > 发送时间:2023-10-31 17:07:11 (星期二)收件人:"Li Xu" > , gcc-patches > 抄送:"kito.cheng" , palmer > , "Li Xu" 主题:Re: [PATCH v6] > RISC-V: Implement

[committed] d: Clean-up unused variable assignments after interface change

Hi, The lowering done for invoking `new' on a single dimension array was moved from the code generator to the front-end semantic pass in r14-4996. This removes the detritus left behind in the code generator from that deletion. Bootstrapped and regression tested on x86_64-linux-gnu/-m32,

Re: [PATCH 2/2] tree-optimization/111131 - SLP for non-IFN gathers

Hi! On 2023-10-19T11:47:14+, Richard Biener wrote: > The following implements SLP vectorization support for gathers > without relying on IFNs being pattern detected (and supported by > the target). That includes support for emulated gathers but also > the legacy x86 builtin path. > >

[PATCH] RISC-V: Support strided load/store

This patch is depending on middle-end patches which are under review. But we can pre-review this patch before the middle-end patch. Consider this following case: void foo (int * __restrict a, int * __restrict b, int stride, int n) { for (int i = 0; i < n; i++) a[i*stride] = b[i*stride]

[PATCH] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize

This patch support loop vectorizer generate direct strided load/store IFN if targets enable it. Note that this patch provide the ability that target enabling strided load/store but without gather/scatter can vectorize stride memory access. gcc/ChangeLog: * optabs-query.cc

[PATCH V2] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN

As previous Richard's suggested, we should support strided load/store in loop vectorizer instead hacking RISC-V backend. This patch adds MASK_LEN_STRIDED LOAD/STORE OPTABS/IFN. The GIMPLE IR is same as mask_len_gather_load/mask_len_scatter_store but with changing vector offset into scalar

Re: Re: [PATCH] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN

Thanks Robin. Address comments on V2. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-10-31 16:45 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; richard.sandiford; rguenther; jeffreyalaw Subject: Re: [PATCH] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN Hi Juzhe, >

Re: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

LGTM from my side. Give kito one more day to review it. Thanks for support this feature ! juzhe.zh...@rivai.ai   From: Li Xu Date: 2023-10-31 17:03 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic From:

[PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

From: xuli Update in v6: * Rename maybe_require_frm_p to may_require_frm_p. * Rename maybe_require_vxrm_p to may_require_vxrm_p. * Move may_require_frm_p and may_require_vxrm_p to function_base. Update in v5: * Split has_vxrm_or_frm_p into maybe_require_frm_p and maybe_require_vxrm_p. *

Re: [PATCH] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN

Hi Juzhe, > +@cindex @code{mask_len_strided_load@var{m}@var{n}} instruction pattern > +@item @samp{mask_len_strided_load@var{m}@var{n}} > +Load several separate memory locations into a vector of mode m. > +Operand 1 is a scalar base address and operand 2 is mode @var{n} > +specifying each uniform

Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

Hi Andrew, Yes and maybe use tree for the type of op_list instead of auto. I suspect this code was originally written before GCC was written in C++11. Maybe if this code is being compiled with C++20 we could do something like: #include template< std::same_as... op_types> To get a decent error

Re: [PATCH] Fix PR ada/111909 On Darwin, determine filesystem case sensitivity at runtime

Hi Simon, (please cc me on Darwin-related patches) > On 29 Oct 2023, at 11:51, Simon Wright wrote: > > This change affects only Ada. > > In gcc/ada/adaint.c(__gnat_get_file_names_case_sensitive), the > assumption for __APPLE__ is that file names are case-insensitive > unless __arm__ or

Re: [PATCH6/8] omp: Reorder call for TARGET_SIMD_CLONE_ADJUST (was Re: [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM)

On Wed, 18 Oct 2023, Andre Vieira (lists) wrote: > This patch moves the call to TARGET_SIMD_CLONE_ADJUST until after the > arguments and return types have been transformed into vector types. It also > constructs the adjuments and retval modifications after this call, allowing > targets to alter

Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

On Tue, Oct 31, 2023 at 12:08 AM Lehua Ding wrote: > > Hi Andrew, > > On 2023/10/31 14:48, Andrew Pinski wrote: > >> +inline > >> +gimple_match_op::gimple_match_op (const gimple_match_cond _in, > >> + code_helper code_in, tree type_in, > >> +

Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

Hi Andrew, On 2023/10/31 14:48, Andrew Pinski wrote: +inline +gimple_match_op::gimple_match_op (const gimple_match_cond _in, + code_helper code_in, tree type_in, + tree op0, tree op1, tree op2, tree op3, +

Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

On Wed, Sep 20, 2023 at 6:10 AM Lehua Ding wrote: > > This patch adds combine cond_len_op and vec_cond to cond_len_op like > cond_op. > > gcc/ChangeLog: > > * gimple-match.h (gimple_match_op::gimple_match_op): > Add interfaces for more arguments. >

Pushed: [PATCH v2] LoongArch: Define HAVE_AS_TLS to 0 if it's undefined [PR112299]

Pushed r14-5030. The subject and ChangeLog are updated to include the PR number. The code change is same as v1. On Mon, 2023-10-30 at 20:44 +0800, chenglulu wrote: > > 在 2023/10/30 下午8:26, Xi Ruoyao 写道: > > On Mon, 2023-10-30 at 19:50 +0800, chenglulu wrote: > > > 在 2023/10/30 下午7:42, Xi

[PATCH 3/4] [PATCH 3/3] Change internal intrin call for AVX512 intrins

gcc/ChangeLog: * config/i386/avx512bf16vlintrin.h (_mm_avx512_castsi128_ps): New. (_mm256_avx512_castsi256_ps): Ditto. (_mm_avx512_slli_epi32): Ditto. (_mm256_avx512_slli_epi32): Ditto. (_mm_avx512_cvtepi16_epi32): Ditto.

[PATCH 2/4] [PATCH 2/3] Change internal intrin call for AVX512 intrins

gcc/ChangeLog: * config/i386/avx512bf16vlintrin.h: Change intrin call. * config/i386/avx512fintrin.h (_mm_avx512_undefined_ps): New. (_mm_avx512_undefined_pd): Ditto. (__attribute__): Change intrin call. * config/i386/avx512vbmivlintrin.h: Ditto.

[PATCH 4/4] Push no-evex512 target for 128/256 bit intrins

gcc/ChangeLog: PR target/111889 * config/i386/avx512bf16intrin.h: Push no-evex512 target. * config/i386/avx512bf16vlintrin.h: Ditto. * config/i386/avx512bitalgvlintrin.h: Ditto. * config/i386/avx512bwintrin.h: Ditto. * config/i386/avx512dqintrin.h:

[PATCH 0/4] Fix no-evex512 function attribute

Hi all, These four patches are going to fix no-evex512 function attribute. The detail of the issue comes following: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111889 My proposal for this problem is to also push "no-evex512" when defining 128/256 intrins in AVX512. Besides, I added some new

Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

Committed, thanks Jeff. On 2023/9/28 6:24, Jeff Law wrote: On 9/20/23 07:09, Lehua Ding wrote: This patch adds combine cond_len_op and vec_cond to cond_len_op like cond_op. gcc/ChangeLog: * gimple-match.h (gimple_match_op::gimple_match_op): Add interfaces for more arguments.

Re: [PATCH 2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases

Committed, thanks Jeff. On 2023/10/17 11:19, Lehua Ding wrote: Hi Jeff, Can you replace riscv_vector with riscv_v?  That way this will still work after Joern commits his change to standardize on the riscv_v target selector. OK with that change, no need to wait for a review on V2, just go