On Fri, Jun 21, 2024 at 5:11 AM Andrew Pinski wrote:
>
> On Thu, Jun 20, 2024 at 7:56 PM liuhongt wrote:
> >
> > Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
> > and x < 0 ? 1 : 0 into (unsigned) x >> 31.
> >
> > Move the optimization did in ix86_expand_int_vcond to match.pd
> >
> > Boots
LGTM
On Fri, Jun 21, 2024 at 9:56 AM Feng Wang
wrote:
> Accroding to the BFloat16 spec, some vector iterators and new pattern
> are added in md files.
>
> All these changes passed the rvv test and rvv-intrinsic test for bfloat16.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add new in
On Thu, Jun 20, 2024 at 11:08 PM Richard Biener wrote:
>
> This applies some maintainance to passes.texi by removing references
> to no longer existing passes. It also fixes a few minor things but
> doesn't fill the gaps that meanwhile exist.
Note this was recorded as https://gcc.gnu.org/bugzill
LGTM
juzhe.zh...@rivai.ai 於 2024年6月21日 週五 12:25 寫道：
> LGTM
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Feng Wang
> *Date:* 2024-06-21 09:54
> *To:* gcc-patches
> *CC:* kito.cheng ; juzhe.zhong
> ; jinma.contrib ; Feng Wang
>
> *Subject:* [PATCH 1/3] RISC-V: Add vec
This applies some maintainance to passes.texi by removing references
to no longer existing passes. It also fixes a few minor things but
doesn't fill the gaps that meanwhile exist.
make pdf tested, pushed.
* doc/passes.texi: Remove references to no longer existing
passes.
---
gcc
On Thu, Jun 20, 2024 at 3:37 PM Richard Sandiford
wrote:
>
> This patch adds a combine pass that runs late in the pipeline.
> There are two instances: one between combine and split1, and one
> after postreload.
>
> The pass currently has a single objective: remove definitions by
> substituting int
> Am 21.06.2024 um 04:35 schrieb Andrew Pinski :
>
> When PAREN_EXPR tree code was added in r0-85884-gdedd42d511b6e4,
> a simplified handling was added to complex lowering. Which means
> we would get:
> ```
> _9 = COMPLEX_EXPR <_15, _14>;
> _11 = ((_9));
> _19 = REALPART_EXPR <_11>;
> _20
On Wed, Oct 25, 2023 at 2:49 AM Richard Sandiford
wrote:
>
> This patch adds a combine pass that runs late in the pipeline.
> There are two instances: one between combine and split1, and one
> after postreload.
>
> The pass currently has a single objective: remove definitions by
> substituting int
+ if (*group.shape == shapes::loadstore
+ || *group.shape == shapes::indexed_loadstore
+ || *group.shape == shapes::vundefined
+ || *group.shape == shapes::misc
+ || *group.shape == shapes::vset
+ || *group.shape == shapes::vget
+ || *group.shape == shapes::vcreate
+
LGTM
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 1/3] RISC-V: Add vector type of BFloat16 format
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin an
From: Pan Li
The zip benchmark of coremark-pro have one SAT_SUB like pattern but
truncated as below:
void test (uint16_t *x, unsigned b, unsigned n)
{
unsigned a = 0;
register uint16_t *p = x;
do {
a = *--p;
*p = (uint16_t)(a >= b ? a - b : 0); // Truncate the result of SAT_SUB
On Thu, Jun 20, 2024 at 7:56 PM liuhongt wrote:
>
> Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
> and x < 0 ? 1 : 0 into (unsigned) x >> 31.
>
> Move the optimization did in ix86_expand_int_vcond to match.pd
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}, aarch64-linux-gnu.
Hi,
Gentle ping.
BR,
Jeff(Jiufu) Guo
Jiufu Guo writes:
> Hi,
>
> Gentle ping ...
>
> Jiufu Guo writes:
>
>> Hi,
>>
>> Gentle ping ...
>>
>> BR,
>> Jeff(Jiufu) Guo
>>
>> Jiufu Guo writes:
>>
>>> Hi,
>>>
>>> 'rlwinm' pattern is already well used for SImode. As this instruction
>>> can touch
Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
and x < 0 ? 1 : 0 into (unsigned) x >> 31.
Move the optimization did in ix86_expand_int_vcond to match.pd
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}, aarch64-linux-gnu.
Ok for trunk?
gcc/ChangeLog:
PR target/114189
Hi,
Gentle ping.
BR,
Jeff(Jiufu) Guo
Jiufu Guo writes:
> Hi,
>
> For PR96866, when printing asm code for modifier "%a", an addressable
> operand is required. While the constraint "X" allow any kind of
> operand even which is hard to get the address directly. e.g. extern
> symbol whose addre
When PAREN_EXPR tree code was added in r0-85884-gdedd42d511b6e4,
a simplified handling was added to complex lowering. Which means
we would get:
```
_9 = COMPLEX_EXPR <_15, _14>;
_11 = ((_9));
_19 = REALPART_EXPR <_11>;
_20 = IMAGPART_EXPR <_11>;
```
In many cases instead of just simply:
``
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin and zvfwma need to be based
on this patch.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (bfloat16_type):
Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX.
Accroding to the BFloat16 spec, some vector iterators and new pattern
are added in md files.
All these changes passed the rvv test and rvv-intrinsic test for bfloat16.
gcc/ChangeLog:
* config/riscv/riscv.md: Add new insn name for vector BFloat16.
* config/riscv/vector-iterators.m
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
Add 'Zvfbfmin' intrinsic in bases.
(class vfwcvtbf16_f): Ditto.
(class
Hi!
Gentle ping^2:
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653339.html
BR,
Kewen
on 2024/6/12 17:35, Kewen.Lin wrote:
> Hi,
>
> Gentle ping:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653339.html
>
> BR,
> Kewen
>
> on 2024/6/3 11:00, Kewen Lin wrote:
>> Joseph poin
Hi Segher,
on 2024/6/21 01:20, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jun 20, 2024 at 06:22:07PM +0800, Kewen.Lin wrote:
>> Following your review comments in [1], this patch is
>> separated from Xionghu's patch v4 [2] and mainly targetted
>> for 32-bit element size, it changes with the gener
On Thu, 2024-06-20 at 14:34 +0100, Richard Sandiford wrote:
>
> I tried compiling at least one target per CPU directory and comparing
> the assembly output for parts of the GCC testsuite. This is just a way
> of getting a flavour of how the pass performs; it obviously isn't a
> meaningful bench
On Thu, 2024-06-20 at 14:34 +0100, Richard Sandiford wrote:
> *minus_plus_one had no constraints, which meant that it could be
> matched after RA with operands 0, 1 and 2 all being different.
> The associated split instead requires operand 0 to be tied to
> operand 1.
Thanks for spotting this.
>
> Then GCC emits the wrong trap instruction, wherever it comes from and
> whatever has caused it. The correct ones for integer division by zero
Thanks so much. It is not the bug of Linux kernel or GCC.
It is a bug of me ;) and qemu.
Qemu didn't pass the code of TEQ correctly; and I haven't ru
Last patch in this round of bitmanip work... At least I think I'm going
to pause here and switch gears to other projects that need attention :-)
This patch introduces the ability to generate bitmanip instructions for
rv64 when operating on SI objects when we know something about the range
of
Hi Richard,
I had a quick look through the patch and noticed a couple of minor typos.
Otherwise looks like a nice cleanup!
On 20/06/2024 14:34, Richard Sandiford wrote:
> rtl-ssa has routines for scanning forwards or backwards for something
> under the control of an exclusion set. These searches
On Linux/x86_64,
9a76db24e044c8058497051a652cca4228cbc8e9 is the first bad commit
commit 9a76db24e044c8058497051a652cca4228cbc8e9
Author: Roger Sayle
Date: Thu Jun 20 16:30:15 2024 +0100
i386: Allow all register_operand SUBREGs in x86_ternlog_idx.
caused
FAIL: gcc.target/i386/pr89984-2.c
On Thu, 20 Jun 2024, Jakub Jelinek wrote:
> 2024-06-19 Jakub Jelinek
> Martin Uecker
>
> PR c/114930
> PR c/115502
> gcc/c/
> * c-decl.cc (c_update_type_canonical): Assert t is main variant
> with 0 TYPE_QUALS. Simplify and don't use check_qualified_type.
>
On Sun, 24 Oct 2004, Roger Sayle wrote:
> It's a long story...
And now even longer...
> However, David Anglin suggested an alternate strategy of subtracting
> max_reg from the stored quantity values themselves. Elaborating on
> that theme, the patch below reorganizes the encoding used for quan
Use INT_MIN rather than -1 in `comparison_qty' where a comparison is not
with a register, because the value of -1 is actually a valid reference
to register 0 in the case where it has not been assigned a quantity.
Using -1 makes `REG_QTY (REGNO (folded_arg1)) == ent->comparison_qty'
comparison
Richard Biener writes:
> On Mon, 17 Jun 2024, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Fri, 14 Jun 2024, Richard Biener wrote:
>> >
>> >> On Fri, 14 Jun 2024, Richard Sandiford wrote:
>> >>
>> >> > Richard Biener writes:
>> >> > > On Fri, 14 Jun 2024, Richard Sandiford wrote
Andi Kleen writes:
PING^3 for the musttail patchkit at
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653319.html
(except the C++ patch which got approved)
Thanks!
-Andi
> Andi Kleen writes:
>
> PING^2
>
>> Need reviewers for the tree and middle-end parts, as well as the C frontend.
>>
Michal Jires writes:
No performance data?
> +
> +static const md5_checksum_t INVALID_CHECKSUM = {
> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +};
There are much faster/optimized modern hashes for good collision detection over
MD5 especially when it's not needed to be cryptographicall
Hi!
On Thu, Jun 20, 2024 at 06:22:07PM +0800, Kewen.Lin wrote:
> Following your review comments in [1], this patch is
> separated from Xionghu's patch v4 [2] and mainly targetted
> for 32-bit element size, it changes with the generic call
> altivec_vmrg*w in vec_widen_[su]mult_{hi,lo}* expanders a
> Am 20.06.2024 um 17:40 schrieb Stefan Schulze Frielinghaus
> :
>
> On Thu, Jun 20, 2024 at 09:06:11AM +0200, Juergen Christ wrote:
>> Some casts were missing leading to missed of bad vectorizations where
>> casting was done scalar followed by a vector creation from the
>> individual element
Hi!
On Wed, Jun 19, 2024 at 08:29:37PM +0200, Jakub Jelinek wrote:
> Right now the patch only supports a single huge string literal in there,
> not concatenation of multiple strings, dunno if we shouldn't add support
> for that so that we don't run into the line length limits for column
> numberin
This introduces testsuite support infra for removing extensions.
Since z* extensions don't have ordering requirements the logic for
adding/removing those extensions has also been consolidated.
This fixes RVWMO compile testcases failing on Ztso targets by removing
the extension from the -march stri
On Thu, Jun 20, 2024 at 09:06:11AM +0200, Juergen Christ wrote:
> Some casts were missing leading to missed of bad vectorizations where
> casting was done scalar followed by a vector creation from the
> individual elements.
>
> gcc/ChangeLog:
>
> * config/s390/vector.md (VEC_HALF_NARROWED):
Tested x86_64-linux.
-- >8 --
libstdc++-v3/ChangeLog:
* include/backward/backward_warning.h: Adjust comments to
suggest as another alternative to .
* include/backward/strstream (strstreambuf, istrstream)
(ostrstream, strstream): Add deprecated attribute.
---
...
Tested x86_64-linux.
-- >8 --
This addresses one known failure due to a bug in the upstream tests, and
a number of timeouts due to the algorithms running much more slowly with
debug mode checks enabled.
libstdc++-v3/ChangeLog:
PR libstdc++/90276
* testsuite/25_algorithms/pstl/al
Tested x86_64-linux.
-- >8 --
These were deprecated in C++17 and std::wstring_convert is planned for
removal in C++26.
libstdc++-v3/ChangeLog:
* include/bits/locale_conv.h (wstring_convert): Add deprecated
attribute for C++17 and later.
(wbuffer_convert): Likewise.
Tested x86_64-linux.
-- >8 --
LWG 3305 was approved earlier this year in Tokyo. We need to give an
error if using std::any_cast, but std::any_cast is valid
(but always returns null).
libstdc++-v3/ChangeLog:
* include/std/any (any_cast(any*), any_cast(const any*)): Add
static ass
Tested x86_64-linux.
-- >8 --
These tests compile very slowly in debug mode.
libstdc++-v3/ChangeLog:
PR libstdc++/90276
* testsuite/25_algorithms/pstl/alg_modifying_operations/rotate_copy.cc:
Increase timeout for debug mode.
*
testsuite/25_algorithms/pstl/alg_mo
Tested x86_64-linux.
-- >8 --
This member function was previously deprecated, but that was reverted by
P2875R4, approved earlier this year in Tokyo. Since it's not going to be
deprecated in C++26, and so presumably not removed, there is no point in
giving deprecated warnings for C++23 mode.
libs
Tested x86_64-linux.
-- >8 --
Dispatching to partial specializations doesn't really seem to offer much
benefit here. The __is_trivial(T) condition is a compile-time constant
so the untaken branches are dead code and don't cost us anything.
libstdc++-v3/ChangeLog:
* include/bits/valarray
Tested x86_64-linux.
-- >8 --
This replaces all uses of the std::__is_pointer type trait with uses of
the new __is_pointer built-in. Since the class template was only used to
enable some performance optimizations for algorithms, we can use the
built-in when __has_builtin(__is_pointer) is true (wh
Tested x86_64-linux.
-- >8 --
This removes the std::__is_void trait, as it conflicts with a Clang
built-in. There is only one use of the trait, which can easily be
replaced by simpler code.
Although Clang has a hack to make the class template work despite using
a reserved name, removing std::__i
We still have __is_arithmetic in after this,
but that needs a lot more work to remove its uses from and
.
Tested x86_64-linux.
-- >8 --
This removes the std::__is_pointer and std::__is_scalar traits, as they
conflicts with a Clang built-in.
Although Clang has a hack to make the class template
We know that valarray's value_type must be DefaultConstructible, so we
don't need to test that. I think __is_trivial is sufficient to tell us
we can use memset to value-initialize the elements.
Tested x86_64-linux.
-- >8 --
This removes the use of the std::__is_scalar trait from ,
where it can b
I think the new conditions are correct. They're certainly an improvment
on just checking __is_scalar without considering what we're assigning it
to.
Tested x86_64-linux.
-- >8 --
As noted in the PR, the optimization used for scalar types in std::fill
and std::fill_n is non-conforming, because it
This unfortunately means we can never increase __cpp_lib_chrono again
for the old string ABI, but I don't see any alternative (except
supporting chrono::tzdb for the old string, which will be a lot of work
that I don't want to do!)
-- >8 --
The header is incomplete for the old std::string ABI, b
> Am 20.06.2024 um 16:05 schrieb Andrew MacLeod :
>
>
>> On 6/20/24 05:31, Richard Biener wrote:
>>> On Thu, 20 Jun 2024, Aldy Hernandez wrote:
>>>
>>> Hi.
>>>
>>> I came around to this, and whipped up the proposed patch. However, it
>>> does seem a bit verbose, and I'm wondering if it's c
On Thu, Jun 13, 2024 at 03:16:44PM +0800, Kewen.Lin wrote:
> Hi,
>
> Gentle ping:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2024-June/653363.html
Hello since this is a treewide update I am not the best person to approve just
this single patch. But it does look good to me as this is what you
On 6/20/24 05:31, Richard Biener wrote:
On Thu, 20 Jun 2024, Aldy Hernandez wrote:
Hi.
I came around to this, and whipped up the proposed patch. However, it
does seem a bit verbose, and I'm wondering if it's cleaner to just
leave things as they are.
The attached patch passes tests and ther
On Thu, 20 Jun 2024, Richard Biener wrote:
> > > The DIV instructions of MIPS won't be trapped themself if the divisor
> > > is zero. The compiler will emit a conditional trap instruct for it.
> > > So the signal will be SIGTRAP instead of SIGFPE.
> >
> > It's an OS kernel bug if you get SIGTRAP
rtl-ssa has routines for scanning forwards or backwards for something
under the control of an exclusion set. These searches are currently
used for two main things:
- to work out where an instruction can be moved within its EBB
- to work out whether recog can add a new hard register clobber
The e
This patch adds a combine pass that runs late in the pipeline.
There are two instances: one between combine and split1, and one
after postreload.
The pass currently has a single objective: remove definitions by
substituting into all uses. The pre-RA version tries to restrict
itself to cases that
The iq2000 test and branch instructions had patterns like:
[(set (pc)
(if_then_else
(eq (and:SI (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "power_of_2_operand" "I"))
(const_int 0))
(match_operand 2 "pc_or_label_ope
All uses of xs_hi_nonmemory_operand allow constraint "i",
which means that they allow consts, symbol_refs and label_refs.
The definition of xs_hi_nonmemory_operand accounted for consts,
but not for symbol_refs and label_refs.
gcc/
* config/stormy16/predicates.md (xs_hi_nonmemory_operand):
*minus_plus_one had no constraints, which meant that it could be
matched after RA with operands 0, 1 and 2 all being different.
The associated split instead requires operand 0 to be tied to
operand 1.
gcc/
* config/sh/sh.md (*minus_plus_one): Add constraints.
---
gcc/config/sh/sh.md | 6 +
No-op moves are given the code NOOP_MOVE_INSN_CODE if we plan
to delete them later. Such insns shouldn't be costed, partly
because they're going to disappear, and partly because targets
won't recognise the insn code.
gcc/
* rtl-ssa/changes.cc (rtl_ssa::changes_are_worthwhile): Don't
This series is a resubmission of the late-combine work. I've fixed
some bugs that Jeff's cross-target CI found last time and some others
that I hit since then.
I've also removed a source of quadraticness (oops!). Doing that
in turn drove some tweaks to the rtl-ssa scan routines.
The complexity
On Thu, Jun 20, 2024 at 1:32 PM Georg-Johann Lay wrote:
>
> cc0 has been removed long ago, removed mentions.
OK
> Johann
>
> diff --git a/htdocs/simtest-howto.html b/htdocs/simtest-howto.html
> index ea69c9ed..f18a78f6 100644
> --- a/htdocs/simtest-howto.html
> +++ b/htdocs/simtest-howto.html
>
On Thu, 20 Jun 2024, Michal Jires wrote:
> This version differs by using INCLUDE_STRING instead of .
> (+whitespace and year)
OK (though I'm not happy to see more std::string use)
Richard.
> ___
>
> This patch implements lockfile used for incremental LTO.
>
> Bootstrapped/regtested on x86_64-
On Sun, Jun 16, 2024 at 9:31 AM Feng Xue OS wrote:
>
> For lane-reducing operation(dot-prod/widen-sum/sad) in loop reduction, current
> vectorizer could only handle the pattern if the reduction chain does not
> contain other operation, no matter the other is normal or lane-reducing.
>
> Actually,
Hi,
On Thu, 20 Jun 2024 at 12:51, Alexandre Oliva wrote:
>
> On Jun 19, 2024, "Richard Earnshaw (lists)" wrote:
>
> > It looks like adding
>
> > if ((unsigned)b[i] >= 8*sizeof (TYPE##BITS##_t)) \
> > __builtin_unreachable(); \
>
> Ah, yes, nice, good idea, than
On Thu, Jun 20, 2024 at 7:47 AM Feng Xue OS wrote:
>
> >> + if (lane_reducing_op_p (op.code))
> >> + {
> >> + unsigned group_size = slp_node ? SLP_TREE_LANES (slp_node) :
> >> 0;
> >> + tree op_type = TREE_TYPE (op.ops[0]);
> >> + tree new_vec
Outside of suggested changes, this version:
- uses #define INCLUDE_*
- is rebased onto current trunk - 'fprintf (mstream,' lines
- --verbose 'recompiling++' count is moved into correct if branch
___
This patch implements Incremental LTO as ltrans cache.
The cache is active when directory $GCC_LT
cc0 has been removed long ago, removed mentions.
Johann
diff --git a/htdocs/simtest-howto.html b/htdocs/simtest-howto.html
index ea69c9ed..f18a78f6 100644
--- a/htdocs/simtest-howto.html
+++ b/htdocs/simtest-howto.html
@@ -164,13 +164,7 @@ to exercise the just-built gcc on every test-suite
in t
Added the following hint on testing for target avr.
Johann
--
diff --git a/htdocs/simtest-howto.html b/htdocs/simtest-howto.html
index 3afbdb0b..ea69c9ed 100644
--- a/htdocs/simtest-howto.html
+++ b/htdocs/simtest-howto.html
@@ -304,5 +304,22 @@ to exercise the just-built gcc on every test-sui
> >else if (ret_elt_bits > arg_elt_bits)
> > modifier = WIDEN;
> >
> > + if (supportable_convert_operation (code, ret_type, arg_type, &code1))
> > +{
> > + g = gimple_build_assign (lhs, code1, arg);
> > + gsi_replace (gsi, g, false);
> > + return;
> > +}
>
> Given
This version differs by using INCLUDE_STRING instead of .
(+whitespace and year)
___
This patch implements lockfile used for incremental LTO.
Bootstrapped/regtested on x86_64-pc-linux-gnu
gcc/ChangeLog:
* Makefile.in: Add lockfile.o.
* lockfile.cc: New file.
* lockfile.
On Thu, Jun 20, 2024 at 12:57 PM Maciej W. Rozycki wrote:
>
> On Thu, 20 Jun 2024, YunQiang Su wrote:
>
> > The DIV instructions of MIPS won't be trapped themself if the divisor
> > is zero. The compiler will emit a conditional trap instruct for it.
> > So the signal will be SIGTRAP instead of SI
On Thu, 20 Jun 2024, YunQiang Su wrote:
> The DIV instructions of MIPS won't be trapped themself if the divisor
> is zero. The compiler will emit a conditional trap instruct for it.
> So the signal will be SIGTRAP instead of SIGFPE.
It's an OS kernel bug if you get SIGTRAP for integer division
On Jun 19, 2024, "Richard Earnshaw (lists)" wrote:
> It looks like adding
> if ((unsigned)b[i] >= 8*sizeof (TYPE##BITS##_t)) \
> __builtin_unreachable(); \
Ah, yes, nice, good idea, thanks!
Here's the patch that implements that, co-attributed to you, as IMHO
On Wed, Jun 19, 2024 at 5:04 AM Roger Sayle wrote:
>
>
> This patch tweaks ix86_ternlog_idx to allow any SUBREG that matches
> the register_operand predicate, and is split out as an independent
> piece of a patch that I have to clean-up redundant ternlog patterns
> in sse.md. It turns out that so
On Tue, 18 Jun 2024 at 07:22, Matthias Kretz wrote:
>
> Tested on x86_64-linux-gnu (also -m32 and -mx32), aarch64-linux-gnu, and arm-
> linux-gnueabi(hf).
>
> OK for trunk and backports? OK, to go for GCC 11.5 as early as possible?
OK for all branches, thanks.
>
> --- 8< ---
Hi Segher,
Following your review comments in [1], this patch is
separated from Xionghu's patch v4 [2] and mainly targetted
for 32-bit element size, it changes with the generic call
altivec_vmrg*w in vec_widen_[su]mult_{hi,lo}* expanders as
well. If this patch looks good to you, I'll post the othe
Hello Richard:
On 19/06/24 3:26 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> On 19/06/24 2:52 pm, Richard Sandiford wrote:
>>> Ajit Agarwal writes:
On 19/06/24 2:40 pm, Richard Sandiford wrote:
> Ajit Agarwal writes:
>> Hello Richard:
>>
>> On 19/06/24 1:54 pm, Ri
Status
==
The gcc-11 branch nears its retirement with the last release from it,
GCC 11.5, on the horizon.
Please look through bugzilla and see which of your regression fixes
for GCC 12 are also applicable for the GCC 11 branch and do the
necessary backporting. Please error on the safe side s
Hello Richard:
All review comments are incorporated.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implement virtual functions defined by generic code.
Target specific code are added in rs6000-mem-fusion.cc.
Bootstrapped and regt
On Thu, 20 Jun 2024, Aldy Hernandez wrote:
> Hi.
>
> I came around to this, and whipped up the proposed patch. However, it
> does seem a bit verbose, and I'm wondering if it's cleaner to just
> leave things as they are.
>
> The attached patch passes tests and there's no difference in
> performa
Status
==
GCC 12.4 has been released and the branch is again open for regression
and documentation fixes.
Quality Data
Priority#Change from last report
------
P1 0
P2588- 31
P3 76- 1
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-06-20 11:28
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Remove integer vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64.
gcc/Chan
This patch deals with consequences but not the root cause though.
There are 5 cases which are subjects to rewrite:
case #1:
mov ip, r1
add r2, ip
# ip is dead here
can be rewritten as:
adds r2, r1
case #2:
add ip, r1
mov r1, ip
# ip is dead here
can be rewritten as:
add r1, ip
ca
From: Eric Botcazou
The code is legal and, therefore, must be accepted by the compiler, but it
must raise Program_Error at run time due to operands not having inferable
discriminants and a warning be given at compile time (RM B.3.3(22-23)).
gcc/ada/
* exp_ch4.adb (Expand_Array_Equality.
From: Eric Botcazou
This was initially implemented as part of AI12-001 but immediately disabled
because it breaks Florist on 32-bit platforms. However, it is possible to
reenable it in almost all cases without affecting Florist, and the -gnatd_l
switch can now be used to disable it again.
gcc/a
From: Bob Duff
...in preparation for implementing type inference for generic
parameters.
The main change is to do the "matching" computation early, and produce a
*constant* data structure (Gen_Assocs_Rec) to represent the matching
between each triple of unanalyzed formal, analyzed formal, and
co
From: Steve Baird
The argument to pragma Extensions_Allowed to enable all extensions is
no longer "All", but instead "All_Extensions".
gcc/ada/
* doc/gnat_rm/gnat_language_extensions.rst: Update documentation.
* doc/gnat_rm/implementation_defined_pragmas.rst: Update
docu
From: Yannick Moy
SPARK RM 6.9(21) forbids a ghost type to have concurrent parts.
This was not enforced, instead only the type itself was checked to
be concurrent. Now fixed.
gcc/ada/
* ghost.adb (Check_Ghost_Type): Fix checking.
Tested on x86_64-pc-linux-gnu, committed on master.
---
From: Gary Dismukes
The compiler crashes on an instantiation of a generic child unit G1.GC
that has a formal private extension P_Ext of a private type P declared
in the parent G1 whose full type has a component C, when analyzing a
selected component ACC.C whose prefix is of an access type coming
From: Piotr Trojanek
Code cleanup; behavior is unaffected.
gcc/ada/
* freeze.adb (Check_Current_Instance): This routine is only called
with parameter E being a type entity, so there is no need to check
for types just before the equality with E.
* sem_ch13.adb (An
From: Yannick Moy
Inlining in GNATprove may fail on a call to a subprogram with a formal
of an array type with fixed lower bound (a GNAT extension), because the
appropriate conversion is not used. Fix it.
Also fix the function that inserts an unchecked conversion, in cases where
it could skip sl
From: Eric Botcazou
In Ada 2012, primitive equality operators of untagged record types compose
like those of tagged record types, but this has never been implemented for
untagged record types with a variant part.
gcc/ada/
* exp_ch4.adb (Expand_Composite_Equality): In the untagged record
From: Steve Baird
In some cases, a reduction expression that references the (nonexistent)
"+" operator of a generic formal private type is incorrectly accepted.
gcc/ada/
* sem_attr.adb (Resolve_Attribute.Proper_Op): When resolving the
name of the reducer subprogram in a reductio
From: Eric Botcazou
The problem is that the freeze node of the type to which the real literal
is resolved is placed inside the expression function instead of outside.
gcc/ada/
* freeze.adb (Freeze_Expression): Also attach pending freeze nodes
to the parent in the case of an inte
From: Eric Botcazou
They are still tailored to Ada 95 while the level of recommended support for
Bit Ordering was changed in Ada 2005.
gcc/ada/
* doc/gnat_rm/implementation_advice.rst (Representation Clauses):
Remove >> marker and add end of sentence after code-block directive.
From: Eric Botcazou
It was implemented apparently because a very early version of AI12-0164
that standardizes GNAT's Max_Queue_Length opted for the subtly different
moniker, but later versions of the AI use Max_Entry_Queue_Length instead.
gcc/ada/
* aspects.ads (Aspect_Id): Remove Aspec
From: Eric Botcazou
The front-end maintains a set of 4 flags on (base) types that are used to
parameterize the implementation of controlled operations, and these flags
need to be propagated through composition and derivation. This is done
on a per-flag basis in the current implementation with a
From: Eric Botcazou
It's an assertion on the name of an instance of a generic child unit and
it needs to cope with a renaming of the unit.
gcc/ada/
* sem_ch12.adb (Instantiate_Formal_Package): Accept renamings of a
generic parent that is a child unit for the abbreviated instance
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