Re: [RFA] [PR rtl-optimization/120553] Improve selecting between constants based on sign bit test

2025-08-18 Thread Richard Biener
On Thu, Aug 14, 2025 at 3:43 PM Jeff Law wrote: > > While working to remove mvconst_internal I stumbled over a regression in > the code to handle signed division by a power of two. > > In that sequence we want to select between 0, 2^n-1 by pairing a sign > bit splat with a subsequent logical right

Re: [PATCH v2 1/2] Match: Add form 3 for unsigned SAT_MUL

2025-08-18 Thread Richard Biener
On Thu, Aug 14, 2025 at 12:08 AM wrote: > > From: Pan Li > > This patch would like to try to match the the unsigned > SAT_MUL form 3, aka below: > > #define DEF_SAT_U_MUL_FMT_3(NT, WT) \ > NT __attribute__((noinline))\ > sat_u_mul_##NT##_from_##WT##_fmt_3 (NT

Re: [PATCH] middle-end: Fix malloc like functions when calling with void "return" [PR120024]

2025-08-18 Thread Richard Biener
On Tue, Aug 19, 2025 at 6:09 AM Andrew Pinski wrote: > > When expanding malloc like functions, we copy the return register into a > temporary > and then mark that temporary register with a noalias regnote and the > alignment. > This works fine unless you are calling the function with a return ty

Re: [PATCH] tree-optimization/121527 - wrong SRA with aggregage copy

2025-08-18 Thread Richard Biener
On Mon, 18 Aug 2025, Richard Biener wrote: > SRA handles outermost VIEW_CONVERT_EXPRs but it wrongly ignores > those when building an access which leads to the wrong size > used when the VIEW_CONVERT_EXPR does not have the same size as > its operand which is valid GENERIC and is used by Ada upcast

Re: [PATCH v3] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread Hongtao Liu
On Tue, Aug 19, 2025 at 10:51 AM H.J. Lu wrote: > > We can't place a TLS call before a conditional jump in a basic block like > > (code_label 13 11 14 4 2 (nil) [1 uses]) > (note 14 13 16 4 [bb 4] NOTE_INSN_BASIC_BLOCK) > (jump_insn 16 14 17 4 (set (pc) > (if_then_else (le (reg:CCNO 17 fla

Re: [PATCH v1 0/1] c: Add support for array parameters in _Countof

2025-08-18 Thread Martin Uecker
Am Montag, dem 18.08.2025 um 23:19 + schrieb Joseph Myers: > On Fri, 15 Aug 2025, Alejandro Colomar wrote: > > > Hi Joseph, > > > > On Thu, Aug 14, 2025 at 10:03:00PM +, Joseph Myers wrote: > > > On Thu, 14 Aug 2025, Alejandro Colomar wrote: > > > > > > > And I'm proposing it as a GNU ex

[PATCH 1/5]middle-end: Add scaffolding to support narrowing IFNs

2025-08-18 Thread Tamar Christina
This adds scaffolding for supporting narrowing IFNs inside the vectorizer in a similar way as how widening is supported. However because narrowing operations always have the same number of elements as the input and output we need to be able to combine the results. One way this could have been don

Re: [PATCH 1/3]AArch64: Fix scalar costing after removal of vectype from mid-end [PR121536]

2025-08-18 Thread Andrew Pinski
On Mon, Aug 18, 2025 at 9:25 PM Tamar Christina wrote: > commit g:fb59c5719c17a04ecfd58b5e566eccd6d2ac583a stops passing the scalar > type > (confusingly named vectype) to the costing hook when doing scalar costing. > > As a result, we could no longer distinguish between FPR and GPR scalar > stmt

[PATCH v1 0/4] RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost

2025-08-18 Thread pan2 . li
From: Pan Li This patch would like to introduce the combine of vec_dup + vmacc.vv into vmacc.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 2, 15 in test. From: | ... | vmv.v.x | L1: | vmacc.vv |

Re: [PATCH v2] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread Hongtao Liu
On Tue, Aug 19, 2025 at 10:55 AM H.J. Lu wrote: > > On Mon, Aug 18, 2025 at 6:56 PM Hongtao Liu wrote: > > > > On Tue, Aug 19, 2025 at 4:40 AM H.J. Lu wrote: > > > > > > On Mon, Aug 18, 2025 at 12:59 AM Hongtao Liu wrote: > > > > > > > > On Mon, Aug 18, 2025 at 4:12 PM Hongtao Liu wrote: > > >

[COMMITTED] testsuite: Fix g++.dg/abi/mangle83.C [PR121578]

2025-08-18 Thread Nathaniel Shead
I'd accidentally had a custom GXX_TESTSUITE_STDS leftover in my environment, so I'd missed testing as C++14. Tested on x86_64-pc-linux-gnu, pushing as obvious. -- >8 -- This testcase (added in r16-3233-g7921bb4afcb7a3) mistakenly only required C++14, but auto template paramaters are a C++17 feat

[PATCH 5/5]middle-end: Use addhn for compression instead of inclusive OR when reducing comparison values

2025-08-18 Thread Tamar Christina
Given a sequence such as int foo () { #pragma GCC unroll 4 for (int i = 0; i < N; i++) if (a[i] == 124) return 1; return 0; } where a[i] is long long, we will unroll the loop and use an OR reduction for early break on Adv. SIMD. Afterwards the sequence is followed by a compression

[PATCH 3/5]AArch64: Add support for addhn vectorizer optabs for Adv.SIMD

2025-08-18 Thread Tamar Christina
This implements the new vector optabs vec_addh_narrow_hi_, vec_addh_narrow_lo_, vec_addh_narrow adding support for in-vectorizer recognition of addhn. The existing codegen tests will now recognize the instructions through the optabs rather than combine. Bootstrapped Regtested on aarch64-none-lin

[PATCH 4/5]middle-end: clear the user unroll flag if the cost model has overriden it

2025-08-18 Thread Tamar Christina
If the user has requested loop unrolling through pragma GCC unroll then at the moment we only set LOOP_VINFO_USER_UNROLL if the vectorizer has not overrode the unroll factor (through backend costing) or if the VF made the requested unroll factor be 1. But of these events are costing related, and s

[PATCH 3/3]AArch64: Use vectype from SLP node instead of stmt_info [PR121536]

2025-08-18 Thread Tamar Christina
commit g:1786be14e94bf1a7806b9dc09186f021737f0227 stops storing in STMT_VINFO_VECTYPE the vectype of the current stmt being vectorized and instead requires the use of SLP_TREE_VECTYPE for everything but data-refs. This means that STMT_VINFO_VECTYPE (stmt_info) will always be NULL and so aarch64_bo

[PATCH 2/5]middle-end: Add detection for add halfing and narrowing instruction

2025-08-18 Thread Tamar Christina
This adds support for detectioon of the ADDHN pattern in the vectorizer. Concretely try to detect _1 = (W)a _2 = (W)b _3 = _1 + _2 _4 = _3 >> (precision(a) / 2) _5 = (N)_4 where W = precision (a) * 2 N = precision (a) / 2 Bootstrapped Regtested on aarch64-none-linux-gnu, arm-none-l

[PATCH 2/3]middle-end: Fix costing hooks of various vectorizable_* [PR121536]

2025-08-18 Thread Tamar Christina
commit g:1786be14e94bf1a7806b9dc09186f021737f0227 stops storing in STMT_VINFO_VECTYPE the vectype of the current stmt being vectorized and instead requires the use of SLP_TREE_VECTYPE for everything but data-refs. However contrary to what the commit says not all usages of STMT_VINFO_VECTYPE have b

[PATCH 1/3]AArch64: Fix scalar costing after removal of vectype from mid-end [PR121536]

2025-08-18 Thread Tamar Christina
commit g:fb59c5719c17a04ecfd58b5e566eccd6d2ac583a stops passing the scalar type (confusingly named vectype) to the costing hook when doing scalar costing. As a result, we could no longer distinguish between FPR and GPR scalar stmts. A later commit also removed STMT_VINFO_VECTYPE from stmt_info. T

[PATCH] middle-end: Fix malloc like functions when calling with void "return" [PR120024]

2025-08-18 Thread Andrew Pinski
When expanding malloc like functions, we copy the return register into a temporary and then mark that temporary register with a noalias regnote and the alignment. This works fine unless you are calling the function with a return type of void. At this point then the valreg will be null and a crash

Re: [PATCH v2] c++: Fix ICE on mangling invalid compound requirement [PR120618]

2025-08-18 Thread Ben Wu
Looks like I mispelled "Merrill". Here is the corrected patch. -Ben On Mon, Aug 18, 2025 at 7:31 PM Ben Wu wrote: > Sorry about that, I'm not sure why the formatting issues are there. > Gmail seems to remove tabs from the patch as well. I attached the > revised patch in case this patch still ha

[PATCH v1 1/4] RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost

2025-08-18 Thread pan2 . li
From: Pan Li This patch would like to combine the vec_duplicate + vmacc.vv to the vmacc.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if th

[PATCH v1 4/4] RISC-V: Adjust the asm check after enable vmacc.vx combine

2025-08-18 Thread pan2 . li
From: Pan Li After enable the vmacc.vx by introducing the define_insn, the below asm need to adjust for this change. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/ternop_vx_constraint-4.c: Adjust asm check for vx. * gcc.target/riscv/rvv/base/ternop_vx_constraint-5

[PATCH v1 3/4] RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15

2025-08-18 Thread pan2 . li
From: Pan Li Add asm dump check and run test for vec_duplicate + vmacc.vvm combine to vmacc.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vx combine. * gcc.target/riscv/rvv/autovec/vx_v

[PATCH v1 2/4] RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15

2025-08-18 Thread pan2 . li
From: Pan Li Add asm dump check and run test for vec_duplicate + vmacc.vvm combine to vmacc.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check for vx combine. * gcc.target/riscv/rvv/autovec/vx_v

Re: [PATCH v2] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread H.J. Lu
On Mon, Aug 18, 2025 at 6:56 PM Hongtao Liu wrote: > > On Tue, Aug 19, 2025 at 4:40 AM H.J. Lu wrote: > > > > On Mon, Aug 18, 2025 at 12:59 AM Hongtao Liu wrote: > > > > > > On Mon, Aug 18, 2025 at 4:12 PM Hongtao Liu wrote: > > > > > > > > On Mon, Aug 18, 2025 at 4:50 AM H.J. Lu wrote: > > >

[PATCH v3] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread H.J. Lu
We can't place a TLS call before a conditional jump in a basic block like (code_label 13 11 14 4 2 (nil) [1 uses]) (note 14 13 16 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (jump_insn 16 14 17 4 (set (pc) (if_then_else (le (reg:CCNO 17 flags) (const_int 0 [0])) (label_ref

Re: [PATCH v2] c++: Fix ICE on mangling invalid compound requirement [PR120618]

2025-08-18 Thread Ben Wu
Sorry about that, I'm not sure why the formatting issues are there. Gmail seems to remove tabs from the patch as well. I attached the revised patch in case this patch still has some formatting problems like the indentation for error_at. I have adjusted the testcases to use dg-prune-output and boot

[PATCHv9] libstdc++: Add generate_canonical impl (P0952, LWG2524) [PR119739]

2025-08-18 Thread Nathan Myers
Changes in v9: * Split out implementations from public pre-26 and 26 APIs. * Add remaining support for non-radix2 float types in C++26. * Handle pow() and floor() compatibly with non-built-in types, and Clang. * Add testing for a non-radix2 float type. * Iron out gratuitous differences between

Re: [PATCH v2] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread Hongtao Liu
On Tue, Aug 19, 2025 at 4:40 AM H.J. Lu wrote: > > On Mon, Aug 18, 2025 at 12:59 AM Hongtao Liu wrote: > > > > On Mon, Aug 18, 2025 at 4:12 PM Hongtao Liu wrote: > > > > > > On Mon, Aug 18, 2025 at 4:50 AM H.J. Lu wrote: > > > > > > > > We can't place a TLS call before a conditional jump in a b

Re: [pushed] [PATCH 00/17] LoongArch: Clean up atomic operations and implement 16-byte atomic operations

2025-08-18 Thread Lulu Cheng
在 2025/8/18 下午7:28, Xi Ruoyao 写道: On Mon, 2025-08-18 at 11:10 +0800, Xi Ruoyao wrote: On Mon, 2025-08-18 at 09:15 +0800, Lulu Cheng wrote: Pushed to r16-3247 ... r16-3264. Sorry it took so long to merge.    LoongArch: Implement 16-byte CAS with sc.q Sorry but it seems we need to revert th

Re: [PATCH v1 0/1] c: Add support for array parameters in _Countof

2025-08-18 Thread Joseph Myers
On Fri, 15 Aug 2025, Alejandro Colomar wrote: > Hi Joseph, > > On Thu, Aug 14, 2025 at 10:03:00PM +, Joseph Myers wrote: > > On Thu, 14 Aug 2025, Alejandro Colomar wrote: > > > > > And I'm proposing it as a GNU extension, which means we don't even need > > > to care about what ISO C says abo

Re: [PATCH v2] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread H.J. Lu
On Mon, Aug 18, 2025 at 12:59 AM Hongtao Liu wrote: > > On Mon, Aug 18, 2025 at 4:12 PM Hongtao Liu wrote: > > > > On Mon, Aug 18, 2025 at 4:50 AM H.J. Lu wrote: > > > > > > We can't place a TLS call before a conditional jump in a basic block like > > > > > > (code_label 13 11 14 4 2 (nil) [1 us

Re: [PATCH v2] c++: Fix ICE on mangling invalid compound requirement [PR120618]

2025-08-18 Thread Jason Merrill
On 8/16/25 2:02 PM, Ben Wu wrote: This testcase caused an ICE when mangling the invalid type-constraint in write_requirement since write_type_constraint expects a TEMPLATE_TYPE_PARM. Setting the trailing return type to NULL_TREE when a return-type-requirement is found in place of a type-constrai

Re: [PATCH] c++/modules: Fix exporting using-decls of unattached purview functions [PR120195]

2025-08-18 Thread Jason Merrill
On 8/16/25 11:06 PM, Nathaniel Shead wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? OK. -- >8 -- We have logic to adjust a function decl if it gets re-declared as a using-decl with different purviewness, but we also need to do the same if it gets redeclared with diff

Re: [PATCH] testsuite: Fix PR108080 testcase for some targets [PR121396]

2025-08-18 Thread Jason Merrill
On 8/16/25 11:13 PM, Nathaniel Shead wrote: Tested on x86_64-pc-linux-gnu and verified with a powerpc64-linux-gnu cross. OK for trunk and 15? OK (obvious) -- >8 -- I added a testcase for the (temporary) warning that we don't currently support the 'gnu::optimize' or 'gnu::target' attributes

Re: [PATCH] c++: constrained corresponding using from partial spec [PR121351]

2025-08-18 Thread Jason Merrill
On 8/18/25 11:36 AM, Patrick Palka wrote: Bootstrapped anh regtested on x86_64-pc-linux-gnu, does this look OK for trunk and 15? OK. -- >8 -- When a using refers to a member from a partial specialization, we need to substitute the arguments relative to partial specialization into the constra

[PUSHED] docs: Fix __builtin_object_size example [PR121581]

2025-08-18 Thread Andrew Pinski
This example used to work (with C) in GCC 14 before the warning for different pointer types without a cast was changed to an error. The fix is to make the q variable `int*` rather than the current `char*`. This also fixes the example for C++ too. Pushed as obvious after doing a `make html`. gcc/C

Re: [PATCH v2 1/2] testsuite: arm: remove arm32 check from a few effective-targets

2025-08-18 Thread Christophe Lyon
On Mon, 18 Aug 2025 at 19:24, Christophe Lyon wrote: > > A few arm effective-targets call check_effective_target_arm32 even > though they would force a -march=XXX flag which supports Arm and/or > Thumb-2, thus making the arm32 check useless. This has an impact when > the toolchain is configured w

[PATCH v2] arm: always enable both simd and mve builtins

2025-08-18 Thread Christophe Lyon
We get lots of error messages when compiling arm_neon.h under e.g. -mcpu=cortex-m55, because Neon builtins are enabled only when !TARGET_HAVE_MVE. This has been the case since MVE support was introduced. This patch uses an approach similar to what we do on aarch64, but only partially since Neon i

[PATCH v2 1/2] testsuite: arm: remove arm32 check from a few effective-targets

2025-08-18 Thread Christophe Lyon
A few arm effective-targets call check_effective_target_arm32 even though they would force a -march=XXX flag which supports Arm and/or Thumb-2, thus making the arm32 check useless. This has an impact when the toolchain is configured with a default -march or -mcpu which supports Thumb-1 only: in su

[PATCH v2 2/2] testsuite: arm: factorize arm_v8_neon_ok flags

2025-08-18 Thread Christophe Lyon
Like we do in other effective-targets, add "-mcpu=unset -march=armv8-a" directly when setting et_arm_v8_neon_flags in arm_v8_neon_ok_nocache, to avoid having to add these two flags in all users of arm_v8_neon_ok. This avoids duplication and possible typos / oversights. gcc/testsuite/ChangeLog:

[PATCH v4] [aarch64] Make better use of overflowing operations in max/min(a, add/sub(a, b)) [PR116815]

2025-08-18 Thread dhruvc
From: Dhruv Chawla This patch folds the following patterns: - umax (a, add (a, b)) -> [sum, ovf] = adds (a, b); !ovf ? sum : a - umin (a, add (a, b)) -> [sum, ovf] = adds (a, b); !ovf ? a : sum - umax (a, sub (a, b)) -> [diff, ovf] = subs (a, b); ovf ? diff : a - umin (a, sub (a, b)) -> [diff,

Re: [PATCH v1] rs6000: Restore opaque overload variant for correct diagnostics

2025-08-18 Thread Kishan Parmar
Ping! please review. Thanks & Regards Kishan On 05/06/25 12:36 pm, Kishan Parmar wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > After r12-5752-gd08236359eb229, a new bif infrastructure was introduced > which stopped using opaque vector typ

[PATCH] c++: constrained corresponding using from partial spec [PR121351]

2025-08-18 Thread Patrick Palka
Bootstrapped anh regtested on x86_64-pc-linux-gnu, does this look OK for trunk and 15? -- >8 -- When a using refers to a member from a partial specialization, we need to substitute the arguments relative to partial specialization into the constraints, not those relative to the primary template. O

Re: [PATCH v4 2/9] opts: use sanitize_code_type for sanitizer flags

2025-08-18 Thread Claudiu Zissulescu-Ianculescu
>> + { NULL, 0ULL, 0UL, false, false } > > sanitize_code_type (0) (or just 0) instead of 0ULL. Same for the other > uses of the same constants. > > OK with that change, thanks. > > Richard > Patch pushed including indicated mods. Thank you, Claudiu

Re: [PATCH v4 4/9] aarch64: add new constants for MTE insns

2025-08-18 Thread Claudiu Zissulescu-Ianculescu
>> + (const_int MEMTAG_TAG_MASK)) ;; 0xf0ff... > > I think we can drop the comments now, since the name of the constant > makes it clear enough. Same for the uses below. > > OK with that change. Thanks for doing this. > > Richard Patch pushed with the additional mods. Thank you,

Re: [PATCH] libstdc++: Cleaned up string_vector_iterators.cc test [PR104874]

2025-08-18 Thread Jonathan Wakely
On Mon, 18 Aug 2025 at 15:40, Jonathan Wakely wrote: > > On Thu, 24 Jul 2025 at 08:33, Tomasz Kamiński wrote: > > > > Removed the wrong_stuff() function, which was effectively empty for > > actual test runs. Replaced the manual failure counter with the VERIFY > > macro to simplify identifying fai

Re: [PATCH] libstdc++: Cleaned up string_vector_iterators.cc test [PR104874]

2025-08-18 Thread Jonathan Wakely
On Thu, 24 Jul 2025 at 08:33, Tomasz Kamiński wrote: > > Removed the wrong_stuff() function, which was effectively empty for > actual test runs. Replaced the manual failure counter with the VERIFY > macro to simplify identifying failures. > > PR libstdc++/104874 > > libstdc++-v3/ChangeLog:

[PATCH] tree-optimization/121527 - wrong SRA with aggregage copy

2025-08-18 Thread Richard Biener
SRA handles outermost VIEW_CONVERT_EXPRs but it wrongly ignores those when building an access which leads to the wrong size used when the VIEW_CONVERT_EXPR does not have the same size as its operand which is valid GENERIC and is used by Ada upcasting. Bootstrapped on x86_64-unknown-linux-gnu with

[PATCH] RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE macros with target hooks

2025-08-18 Thread Kito Cheng
The FUNCTION_VALUE and LIBCALL_VALUE macros are deprecated in favor of the TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE target hooks. This patch replaces the macro definitions with proper target hook implementations. This change is also a preparatory step for VLS calling convention support, whi

Re: [pushed] [PATCH 00/17] LoongArch: Clean up atomic operations and implement 16-byte atomic operations

2025-08-18 Thread Xi Ruoyao
On Mon, 2025-08-18 at 11:10 +0800, Xi Ruoyao wrote: > On Mon, 2025-08-18 at 09:15 +0800, Lulu Cheng wrote: > > Pushed to r16-3247 ... r16-3264. > > > > Sorry it took so long to merge. > > > >    LoongArch: Implement 16-byte CAS with sc.q > > Sorry but it seems we need to revert this one particul

RE: [GCC 15] aarch64: Fix mode mismatch when building a predicate [PR121118]

2025-08-18 Thread Tamar Christina
> -Original Message- > From: Richard Sandiford > Sent: Monday, August 18, 2025 11:30 AM > To: gcc-patches@gcc.gnu.org > Cc: Alex Coplan ; Alice Carlotti > ; > pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw > ; Tamar Christina ; > Wilco Dijkstra > Subject: [GCC 15] aarch64: F

RE: [v2] PR81358: Enable automatic linking of libatomic

2025-08-18 Thread Prathamesh Kulkarni
> -Original Message- > From: Prathamesh Kulkarni > Sent: 10 August 2025 20:04 > To: Matthew Malcomson ; gcc-patches@gcc.gnu.org > Cc: Joseph Myers ; Thomas Schwinge > ; Sam James > Subject: RE: [v2] PR81358: Enable automatic linking of libatomic > > External email: Use caution opening

[GCC 15] aarch64: Fix mode mismatch when building a predicate [PR121118]

2025-08-18 Thread Richard Sandiford
This PR is about a case where we used aarch64_expand_sve_const_pred_trn to combine two predicates, one of which was constructing using aarch64_sve_move_pred_via_while. The former requires the inputs to have mode VNx16BI, but the latter returned VNx8BI for a .H WHILELO. The proper fix, used on tru

Re: [PATCH] gcse: Fix handling of partial clobbers [PR97497]

2025-08-18 Thread Richard Sandiford
Richard Biener writes: > On Mon, Aug 18, 2025 at 10:51 AM Richard Sandiford > wrote: >> >> This patch fixes an internal disagreement in gcse about how to >> handle partial clobbers. Like many passes, gcse doesn't track >> the modes of live values, so if a call clobbers only part of >> a register

Re: [PATCH] libstdc++: Add nodiscard attribute for ranges algorithm [PR121476]

2025-08-18 Thread Jonathan Wakely
On Mon, 18 Aug 2025 at 10:14, Tomasz Kamiński wrote: > > This patch adds the [[nodiscard]] attribute to the operator() of ranges > algorithm function objects if their std counterpart has it. > > Furthermore, we [[nodiscard]] the operator() of the following ranges > algorithms that lack a std counte

[PATCH] libstdc++: Add nodiscard attribute for ranges algorithm [PR121476]

2025-08-18 Thread Tomasz Kamiński
This patch adds the [[nodiscard]] attribute to the operator() of ranges algorithm function objects if their std counterpart has it. Furthermore, we [[nodiscard]] the operator() of the following ranges algorithms that lack a std counterpart: * find_last, find_last_if, find_last_if_not (to match oth

Re: [PATCH] gcse: Fix handling of partial clobbers [PR97497]

2025-08-18 Thread Richard Biener
On Mon, Aug 18, 2025 at 10:51 AM Richard Sandiford wrote: > > This patch fixes an internal disagreement in gcse about how to > handle partial clobbers. Like many passes, gcse doesn't track > the modes of live values, so if a call clobbers only part of > a register, the pass has to make conservati

[PATCH] gcse: Fix handling of partial clobbers [PR97497]

2025-08-18 Thread Richard Sandiford
This patch fixes an internal disagreement in gcse about how to handle partial clobbers. Like many passes, gcse doesn't track the modes of live values, so if a call clobbers only part of a register, the pass has to make conservative assumptions. As the comment in the patch says, this means: (1) ig

Re: [PATCH v2 0/4] implement defer statements as per ts 25755

2025-08-18 Thread Anna (navi) Figueiredo Gomes
> * moved the 'defer' keyword behind a -fdefer-ts flag, and added texinfo > docs plus related failure test. it was mentioned to me that having both -std=c2y and -fdefer-ts would be excessive. i'll wait a bit for more feedback, then send a v3 dropping 1/4 and adjusting the following commits to remo

[commited v3] libstdc++: Fix-self element self-assigments when inserting an empty range [PR121313]

2025-08-18 Thread Tomasz Kamiński
For __n == 0, the elements were self move-assigned by std::move_backward(__ins, __old_finish - __n, __old_finish). PR libstdc++/121313 libstdc++-v3/ChangeLog: * include/bits/vector.tcc (vector::insert_range): Add check for empty size. * testsuite/23_containers/vec

Re: [PATCH v2] [x86] Enable unroll in the vectorizer when there's reduction for FMA/DOT_PROD_EXPR/SAD_EXPR

2025-08-18 Thread Hongtao Liu
On Mon, Aug 11, 2025 at 8:57 PM Richard Biener wrote: > > On Sun, 10 Aug 2025, liuhongt wrote: > > > > > > > The comment doesn't match the bool type. > > > > > Fixed. > > > > > > > > is_gimple_assign (stmt_info->stmt) > > > > > Changed. > > > > > There's also SAD_EXPR? The vectorizer has lane_red

[RFC PATCH v2] [AutoFDO] Source filename tracking in GCOV

2025-08-18 Thread dhruvc
From: Dhruv Chawla This patch is a respin of the RFC originally posted at https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686835.html. The patch reads the file names from the GCOV file and compares them against DECL_SOURCE_FILE for symbols to decide which profile count to annotate them with.

Re: [PATCH] libstdc++: Fix-self element self-assigments when insertint an empty range [PR121313]

2025-08-18 Thread Tomasz Kaminski
The overlapping range, will lead to move from moved-from object, which I think is generally expected to work. My preference is to land this fix for us misbehaving for correct inputs, and consider any additional assertions separately. On Fri, Aug 15, 2025 at 12:27 PM Jonathan Wakely wrote: > Mayb

Re: [PATCH v2] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread Hongtao Liu
On Mon, Aug 18, 2025 at 4:12 PM Hongtao Liu wrote: > > On Mon, Aug 18, 2025 at 4:50 AM H.J. Lu wrote: > > > > We can't place a TLS call before a conditional jump in a basic block like > > > > (code_label 13 11 14 4 2 (nil) [1 uses]) > > (note 14 13 16 4 [bb 4] NOTE_INSN_BASIC_BLOCK) > > (jump_ins

Re: [PATCH v2] x86: Place the TLS call before all register setting BBs

2025-08-18 Thread Hongtao Liu
On Mon, Aug 18, 2025 at 4:50 AM H.J. Lu wrote: > > We can't place a TLS call before a conditional jump in a basic block like > > (code_label 13 11 14 4 2 (nil) [1 uses]) > (note 14 13 16 4 [bb 4] NOTE_INSN_BASIC_BLOCK) > (jump_insn 16 14 17 4 (set (pc) > (if_then_else (le (reg:CCNO 17 flag