ence other targets.
Do you have other ideas to fix this issue? Or such patch with adding
adjust_precision support is OK to GCC?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford<mailto:richard.sandif...@arm.com>
Date: 2023-03-01 20:03
To: 盼 李 via Gcc-pa
4BI Before precision [0x4, 0x4], size [0x4, 0]
VNx4BI After precision [0x4, 0x4], size [0x4, 0]
Pan
From: Richard Sandiford
Sent: Wednesday, March 1, 2023 19:11
To: 盼 李 via Gcc-patches
Cc: juzhe.zh...@rivai.ai ; pan2.li ; 盼
李 ; Kito.cheng ;
rguenther
Subject: Re:
: Richard Sandiford
Sent: Wednesday, March 1, 2023 19:11
To: 盼 李 via Gcc-patches
Cc: juzhe.zh...@rivai.ai ; pan2.li ; 盼
李 ; Kito.cheng ;
rguenther
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
盼 李 via Gcc-patches writes:
> Thank you all for your quick response.
Thank you all for your quick response.
As juzhe mentioned, the memory access of RISC-V will be always aligned to the
bytes boundary with the compact mode, aka ceil(vl / 8) bytes for vbool*.
Actually, the data [4,4] comes from the self-test, the RISC-V precision mode as
below.
VNx64BI precision
Understood, thanks for the explanations and suggestions. Let me have a try and
keep you posted.
Pan
From: Richard Sandiford
Sent: Tuesday, February 28, 2023 17:50
To: Li, Pan2
Cc: 盼 李 ; incarnation.p.lee--- via Gcc-patches
; juzhe.zh...@rivai.ai ;
kito.ch...@s
Never mind, wish you have a good holiday.
Thanks for pointing this out, the if part cannot take care of poly_int with N >
2. As I understand, we need to make it general for all the N of poly_int.
Thus I would like to double confirm with you about how to make it general. I
suppose there will be
Hi all,
Thank you for your patience. Just file another PR like "Bugfix for rvv bool
mode precision adjustment" for the mode precision adjustment only. Feel free to
comment if any questions or concerns.
Pan
From: 盼 李
Sent: Wednesday, February 15, 2023 23:57
To:
After some investigation, the mode precision adjusting can help to tell the
difference from the VxN1BI to VxN64BI, besides the existing mode_size. Thus I
would like to prepare the patch for the precision adjustment only first.
Unfortunately, there is one selftest failure right now when I try to
Thanks all for your help and comments.
Let me share more information about this patch. Especially for the
tree-ssa-sccvn.cc part.
Assume we have the blow test code for this issue.
void
test_1(int8_t * restrict in, int8_t * restrict out) {
vbool8_t v2 = *(vbool8_t*)in;
vbool16_t v5 = *(v
