[PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

These tests check the sched2 dump, so skip them for optimization levels that do not enable sched2. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-6.c: Skip for -O0, -O1, -Og. * gcc.target/riscv/mcpu-7.c: Likewise. --- gcc/testsuite/gcc.target/riscv/mcpu-6.c | 1 + gcc/testsuite

Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass

On 12/05/2020 23:33, Jim Wilson wrote: > On Mon, Apr 27, 2020 at 10:08 AM Craig Blackmore > wrote: >> Thanks for the review. I have updated the following patch with those changes. > This looks good, and the tree is open for development work again, so I > committed both parts 1 a

Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass

On 08/04/2020 17:04, Jim Wilson wrote: > On Wed, Feb 19, 2020 at 3:40 AM Craig Blackmore > wrote: >> On 10/12/2019 18:28, Craig Blackmore wrote: >> Thank you for your review. I have posted an updated patch below which I think >> addresses your comments. >> >&g

Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass

On 10/12/2019 18:28, Craig Blackmore wrote: > > Hi Jim, > > Thank you for your review. I have posted an updated patch below which I think > addresses your comments. > Ping https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00712.html https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00713.html Craig

Re: [PATCH v2 2/2] sched-deps.c: Avoid replacing address if it increases address cost

Hi Jim, On 31/10/2019 00:03, Jim Wilson wrote: > On Fri, Oct 25, 2019 at 10:40 AM Craig Blackmore > wrote: >> The sched2 pass undoes some of the addresses generated by the RISC-V >> shorten_memrefs code size optimization (patch 1/2) and consequently increases >> code s

Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass

Hi Jim, Thank you for your review. I have posted an updated patch below which I think addresses your comments. On 30/10/2019 23:57, Jim Wilson wrote: > On Fri, Oct 25, 2019 at 10:40 AM Craig Blackmore > wrote: >> This patch aims to allow more load/store instructions to be c

[PATCH v2 1/2] RISC-V: Add shorten_memrefs pass

This patch aims to allow more load/store instructions to be compressed by replacing a load/store of 'base register + large offset' with a new load/store of 'new base + small offset'. If the new base gets stored in a compressed register, then the new load/store can be compressed. Since there is an o

[PATCH v2 2/2] sched-deps.c: Avoid replacing address if it increases address cost

The sched2 pass undoes some of the addresses generated by the RISC-V shorten_memrefs code size optimization (patch 1/2) and consequently increases code size. This patch prevents sched-deps.c from changing an address if it is expected to increase address cost. Tested on bare metal rv32i, rv32iac, r

[PATCH v2 0/2] RISC-V: Allow more load/stores to be compressed

reg so that increase code size? > Before reload, we do not know whether the base reg will be a compressed register or not. > > On Fri, Sep 13, 2019 at 12:20 AM Craig Blackmore > wrote: >> >> This patch aims to allow more load/store instructions to be compressed by >

[PATCH] RISC-V: Allow more load/stores to be compressed

This patch aims to allow more load/store instructions to be compressed by replacing a load/store of 'base register + large offset' with a new load/store of 'new base + small offset'. If the new base gets stored in a compressed register, then the new load/store can be compressed. Since there is an o