Re: patch to fix a wrong code generation with LRA when SDmode is used on ppc.

Hi, Vlad Why does rs6000_emit_move need special support for SDmode with LRA and not with reload? In other words, why is this a specific fix for rs6000 instead of a general improvement for reload? SDmode has some bizarre restrictions on PPC, but one of the historical advantages of GCC was reload'

Re: [PATCH powerpc64] Add a new constraint to insn movdi_internal64

On Fri, Aug 8, 2014 at 1:50 PM, Carrot Wei wrote: > Thank you for the comment, I've updated the patch. > > OK for trunk and 4.9 branch? > > > 2014-08-08 Guozhi Wei > > * config/rs6000/rs6000.md (*movdi_internal64): Add a new constraint. > > > On Wed, Aug 6, 2014 at 7:28 PM, Segher Boess

Re: [PATCH], rs6000 cleanup, make constraints tighter

On Thu, Aug 7, 2014 at 2:41 PM, Michael Meissner wrote: > I'm starting to look at updating my old address branch with an eye towards > getting the changes committed in GCC 4.10. The address branch is meant to > rewrite handling of addresses in the rs6000 backend, to generalize the > addresses bef

Re: patch to fix a wrong code generation with LRA when SDmode is used on ppc.

Hi, Vlad Thanks for the explanation. The patch is okay. Thanks, David On Fri, Aug 8, 2014 at 5:26 PM, Vladimir Makarov wrote: > On 2014-08-08, 2:53 PM, David Edelsohn wrote: >> >> Hi, Vlad >> >> Why does rs6000_emit_move need special support for SDmode with

Re: [PATCH 0/4] rs6000: Merge most logical SI and DI patterns

I wish that this patch did not need to use up another one of the primary constraint letters, but I guess there is no easy way around that. - David On Fri, Aug 15, 2014 at 8:50 PM, Segher Boessenkool wrote: > All patches were bootstrapped and regression checked separately, on > powerpc64-linux -m

Re: [PATCH,rs6000] Add pass to optimize away xxpermdi's from vector computations

On Wed, Aug 13, 2014 at 7:14 PM, Bill Schmidt wrote: > Hi, > > This patch adds a PowerPC-specific pass just prior to the first cse RTL > pass. The pass runs only when generating little-endian code for Power8 > with VSX enabled, and for -O1 and up. For this particular subtarget, > the use of the

Re: [PATCH 2/4] rs6000: Merge boolcsi3 and boolcdi3

On Fri, Aug 15, 2014 at 8:50 PM, Segher Boessenkool wrote: > 2014-08-15 Segher Boessenkool > > gcc/ > * config/rs6000/rs6000.md (*boolcsi3_internal1, *boolcsi3_internal2 > and split, *boolcsi3_internal3 and split): Delete. > (*boolcdi3_internal1, *boolcdi3_internal2 and

Re: [PATCH 1/4] rs6000: Merge boolsi3 and booldi3

On Fri, Aug 15, 2014 at 8:50 PM, Segher Boessenkool wrote: > This adds a new output modifier "e" that prints an 's' for things like > xoris, and changes "u" to work for both xoris and xori. With that, both > SI and DI can simply use an "n" constraint, where previously they needed > "K,L" resp. "K

Re: [PATCH 3/4] rs6000: Merge boolccsi3 and boolccdi3

On Fri, Aug 15, 2014 at 8:50 PM, Segher Boessenkool wrote: > 2014-08-15 Segher Boessenkool > > gcc/ > * config/rs6000/rs6000.md (*boolccsi3_internal1, *boolccsi3_internal2 > and split, *boolccsi3_internal3 and split): Delete. > (*boolccdi3_internal1, *boolccdi3_internal2

Re: [PATCH 4/4] rs6000: Merge andsi3 and anddi3

On Fri, Aug 15, 2014 at 8:50 PM, Segher Boessenkool wrote: > "AND" is more complex. It was a huge tangled mess, where very often the > order of patterns mattered. > > So I made most patterns mutually exclusive (via their condition), and also > made the "S" constraint (for mask64_operand) require

Re: [PATCH,rs6000] Add pass to optimize away xxpermdi's from vector computations

On Sun, Aug 17, 2014 at 8:39 PM, Bill Schmidt wrote: > On Sun, 2014-08-17 at 14:52 -0400, David Edelsohn wrote: >> On Wed, Aug 13, 2014 at 7:14 PM, Bill Schmidt >> wrote: >> > Hi, >> > >> > This patch adds a PowerPC-specific pass just prior to the fi

Re: [PATCH,rs6000] Add __VEC_ELEMENT_REG_ORDER__ builtin define for PowerPC

2014-08-15 Bill Schmidt * conifg/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Provide builtin define __VEC_ELEMENT_REG_ORDER__. Okay. Thanks, David

Re: [PATCH, rs6000] Enable and document some additional builtin overloads

On Wed, Aug 20, 2014 at 8:41 PM, Bill Schmidt wrote: > Hi, > > The Power ISA 2.07 enables some additional forms of existing vector > builtins, in particular allowing use of vector long long (signed and > unsigned) and vector double forms. This patch adds those builtins and > provides documentatio

Re: [PATCH, rs6000] PR 62195, Fix wi constraint

On Thu, Aug 21, 2014 at 3:30 PM, Michael Meissner wrote: > (I'm not sure if an earlier patch got mailed out, I'm sorry if there are > duplicate postings). > > I had a thinko in my patch on August 11th, in that I allowed the wi constraint > to be FLOAT_REGS on a non-VSX system, but I had a pattern

Re: [BUILDROBOT][PATCH] ppc{,64}-linux broken (IPA C++ refactoring 4/N)

2014-08.25 Jan-Benedict Glaw * config/rs6000/rs6000.c (rs6000_return_in_msb): Fix fallout from cgraph_state conversion. The patch seems reasonable to me based on the other changes. Thanks, David

Re: [PATCH,rs6000] Add some more vector built-ins

On Tue, Aug 26, 2014 at 7:52 PM, Bill Schmidt wrote: > Hi, > > This patch adds a few more cases of overloaded vector built-ins to > support V2DI and V2DF modes: vec_xl, vec_xst, vec_splat, vec_div, > vec_mul, vec_round. These are all straightforward. For vec_div and > vec_mul, the most efficien

Re: [PATCH] GCC/test: Disable loop-19.c for classic FPU Power

On Fri, Aug 29, 2014 at 10:46 PM, Maciej W. Rozycki wrote: > Hi, > > The loop-19.c test case has regressed from 4.8 to 4.9 and trunk on > classic FPU Power targets, these failures are now seen: > > FAIL: gcc.dg/tree-ssa/loop-19.c scan-tree-dump-times optimized "MEM.(base: > &|symbol: )a," 2 > FA

Re: [PATCH, rs6000] A few more vector builtins

On Fri, Aug 29, 2014 at 2:28 PM, Bill Schmidt wrote: > Hi, > > This is the last in the current series of new vector built-ins. This > group adds vec_ctf, vec_cts, and vec_ctu for vector double and vector > long long. Additionally, it adds documentation for the built-ins added > in my last patch,

Re: [PATCH 1/4] rs6000: Merge mulsi3 and muldi3

On Mon, Sep 1, 2014 at 3:49 PM, Segher Boessenkool wrote: > Nothing noteworthy in this patch, sorry. > > Tested as usual (powerpc64-linux, -m64,-m32,-m32/-mpowerpc64), no > regressions. Is this okay to apply? > > > Segher > > > 2014-09-01 Segher Boessenkool > > gcc/ > * config/rs6000/r

Re: [PATCH 2/4] rs6000: Merge and improve highpart and widening muls

On Mon, Sep 1, 2014 at 3:49 PM, Segher Boessenkool wrote: > This is a little more complex. The highpart muls generate a "truncate > lshiftrt" pattern that is not canonical when widening to two registers, > so this doesn't optimise well with combine. This patch changes it to use > the canonical s

Re: [PATCH 3/4] rs6000: Merge zero_extend*si2 and zero_extend*di2

On Mon, Sep 1, 2014 at 3:49 PM, Segher Boessenkool wrote: > Don't group the insns based on extended size; use source size instead. > Use the "andi." insn rather than "rldicl." and friends if possible. > The instructions guarded by TARGET_LFIWZX do not need that guard: the > constraints already gua

Re: [PATCH 4/4] rs6000: Merge extend*si2 and extend*di2

On Mon, Sep 1, 2014 at 3:49 PM, Segher Boessenkool wrote: > Mostly like zero_extend, with two twists. First, this patch allows to set > "dot" on insn type "exts". Now we are almost ready to remove insn type > "compare". > > Second, this makes lwa_operand reject memory if avoiding Cell microcode.

Re: [PATCH, rs6000] Fix REG_CLASS_CONTENTS

On Tue, May 31, 2011 at 12:08 PM, Pat Haugen wrote: > The following patch fixes an issue I noticed where vr0..vr2 were > inadvertently included in NON_FLOAT_REGS. > > Bootstrap/regtest on powerpc64-linux with no new regressions. Ok for trunk? > > -Pat > > > 2011-05-31  Pat Haugen > >        * con

Re: [PATCH, rs6000] Tidy up dumping of register/memory move cost

On Wed, May 25, 2011 at 3:02 PM, Pat Haugen wrote: > The following fixes a problem when dumping register costs, where the > incorrect 'from' value was being written out because the code modified the > incoming parameter value. It also changes things so that register/memory > costs are only dumped

Re: [PATCH, rs6000] Fix REG_CLASS_CONTENTS

On Fri, Jun 3, 2011 at 8:41 AM, Pat Haugen wrote: > I should have asked before, ok for 4.6 also after bootstrap/regtest? Yes. Thanks, David

Re: AIX net/if_arp.h include fix for struct fc_softc

On Mon, Jun 6, 2011 at 12:16 AM, Peter O'Gorman wrote: > Hi, > > We ran across an issue with qt-4.7 built with gcc-4.4 on AIX 5.2, 5.3, > 6.1, and 7.1 where some static constructors were not being called. It > turned out to be a header file issue, see, for example, > https://www.ibm.com/developerw

Re: powerpc64 large-toc vs. reload

On Sun, Jun 19, 2011 at 10:03 AM, Alan Modra wrote: > I was alerted to a problem with large toc (-mcmodel=medium/large) code > a few days ago by warnings emitted during a binutils build. > > dwarf.c: In function 'display_debug_lines_raw': > dwarf.c:2409:1: note: non-delegitimized UNSPEC UNSPEC_TOC

Re: [PATCH] Fix bootstrap on OpenBSD, PR48851

On Mon, Jul 4, 2011 at 8:51 AM, Richard Guenther wrote: > On Mon, 4 Jul 2011, Bruce Korb wrote: > >> Hi Richard, >> >> On Mon, Jul 4, 2011 at 4:04 AM, Richard Guenther wrote: >> > >> > It happens that OpenBSD suffers from a bogus fixinclude that changes >> > its perfectly valid NULL define from (

Re: [PATCH] Add -mno-r11 option to suppress load of ppc64 static chain in indirect calls

On Wed, Jul 6, 2011 at 6:29 PM, Michael Meissner wrote: > This patch adds an option to not load the static chain (r11) for 64-bit > PowerPC > calls through function pointers (or virtual function).  Most of the languages > on the PowerPC do not need the static chain being loaded when called, and >

Re: [PATCH] Add -mno-r11 option to suppress load of ppc64 static chain in indirect calls

On Thu, Jul 7, 2011 at 11:53 AM, Richard Guenther wrote: > Well, that's up to the target maintainers to decide, maybe > -mno-nested-functions instead? Is -mno-nested-functions or -mno-nested-function-pointers too C-centric or GCC-centric? I don't know what wording would be more informative, but

Re: [PATCH] Fix rs6000 vector select RTL patterns (PR target/49621)

On Fri, Jul 8, 2011 at 8:40 AM, Jakub Jelinek wrote: > Hi! > > As mentioned in the PR, IMNSHO the rs6000 vector_select_* patterns > are invalid RTL, they compare a vector register in some vector mode > to const0_rtx instead of corresponding vector zero constant. > > The "Comparison Operations" sec

Re: [PATCH] Add -mno-r11 option to suppress load of ppc64 static chain in indirect calls

On Thu, Jul 7, 2011 at 4:19 PM, Richard Guenther wrote: > Does XLC have a similar switch whose name we can use? The IBM XL compiler is discussing a similar feature, but it is not implemented yet and does not have a formal command line option name. - David

[PATCH, AIX] Add missing macros PR39950

The appended patch adds a few macros that XLC now defines on AIX. - David * config/rs6000/aix.h (TARGET_OS_AIX_CPP_BUILTINS): Define __powerpc__, __PPC__, __unix__. Index: aix.h === --- aix.h (revision 179610)

Re: Force aliases to be output when cgraph decides so

Honza, I filed PR50689. After your change, the alias is moved from near the end of the file to just before the definition. AIX assembler is a single pass assembler that does not allow forward references. - David On Sun, Sep 25, 2011 at 6:27 AM, Jan Hubicka wrote: >> Jan, >> >> This patch caus

Re: [rs6000] Enable scalar shifts of vectors

On Wed, Oct 12, 2011 at 6:32 PM, Richard Henderson wrote: > I suppose technically the middle-end could be improved to implement > ashl as vashl by broadcasting the scalar, but Altivec > is the only extant SIMD ISA that would make use of this.  All of > the others can arrange for constant shifts to

Re: [rs6000] Enable scalar shifts of vectors

On Wed, Oct 12, 2011 at 6:32 PM, Richard Henderson wrote: > I suppose technically the middle-end could be improved to implement > ashl as vashl by broadcasting the scalar, but Altivec > is the only extant SIMD ISA that would make use of this.  All of > the others can arrange for constant shifts to

Re: PowerPC shrink-wrap support 3 of 3

On Wed, Sep 28, 2011 at 11:47 AM, Alan Modra wrote: >        * config/rs6000/rs6000.c (rs6000_make_savres_rtx): Delete unneeded >        declaration. >        (rs6000_emit_stack_reset): Only return insn emitted when it adjusts sp. >        (rs6000_make_savres_rtx): Rename to rs6000_emit_savres_rt

Re: [Patch]: fix typo in rs6000.c (AIX bootstrap broken)

Tristan, Mike fixed the typo already. Why are you still seeing a problem? - David On Tue, Oct 18, 2011 at 6:52 AM, Tristan Gingold wrote: > Ping… > > On Oct 13, 2011, at 5:11 PM, Tristan Gingold wrote: > >> Hi, >> >> looks like an obvious typo.  Ok for trunk ? >> >> Tristan. >> >> 2011-10-13  

Re: [PATCH 3/6] Emit macro expansion related diagnostics

Hey, Dodji, Your patch broke bootstrap on AIX because of the typedef "loc_t" introduced in tree-diagnostics.c. The typedef conflicts with a typedef in an AIX 5.3 header file for locales. AIX should not be using that namespace, but the failure occurs before fix-includes, so it is not possible to

Re: [Patch] Add support of AIX response files in collect2

On Fri, Oct 21, 2011 at 6:39 AM, Tristan Gingold wrote: > Hi, > > the AIX linker supports response files with the '-fFILE' command line option. > With this patch, collect2 reads the content of the response files and listed > object files are handled.  Therefore these files are not forgotten by th

Re: [PATCH 5/6] rs6000: Remove some vec_extract_even/odd expanders.

On Mon, Oct 24, 2011 at 8:17 PM, Richard Henderson wrote: > The ones that expand to VPERM can be handled by generic code. > The even v4si and v4sf expanders remain until vector.md can be > updated to not invoke them directly. > +;; ??? This is still used directly by vector.md >  (define_expand "v

Re: [PATCH, rs6000] Update Power7 scheduling

On Thu, Oct 27, 2011 at 6:14 PM, Pat Haugen wrote: > The following patch fixes some issues with the Power7 scheduling > description. The patch is neutral on cpu2006 (was actually hoping to see > some improvements, but it's still the right thing to do since it more > accurately describes the hardwa

Re: [PATCH, rs6000] Preserve link stack for 476 cpus

On Fri, Oct 28, 2011 at 12:36 PM, Peter Bergner wrote: > So David, do we even want to bother trying to support this on -m64 > given the only cpu that needs this is a 32-bit only cpu?  If so, I > can try and work with Alan to figure out how we can merge the > function descriptors for the thunk rou

[PATCH] Fix AIX breakage from gcc-ar/nm/ranlib wrappers

This patch breaks bootstrap on AIX because it includes before "config.h". "config.h" header can affect system headers. I am not sure why stdio.h should be included because system.h itself includes . The appended patch moves stdio.h after config.h, but maybe gcc-ar.h should not include stdio.h e

Re: [PATCH, rs6000] Preserve link stack for 476 cpus

On Mon, Oct 31, 2011 at 5:32 PM, Peter Bergner wrote: > Ok, attached below is the updated patch that passes bootstrap and regtesting > that only enables the new link stack code for 32-bit compiles.  However, > talking with Alan, he mentioned we just have to mark the opd entry weak > and that will

Re: [PATCH, rs6000] Preserve link stack for 476 cpus

On Tue, Nov 1, 2011 at 3:00 PM, Peter Bergner wrote: > +/* Fills in the label name that should be used for a 476 link stack thunk.   > */ > + > +void > +get_ppc476_thunk_name (char name[32]) > +{ > +  gcc_assert (TARGET_LINK_STACK); > + > +  if (HAVE_GAS_HIDDEN) > +    sprintf (name, "__ppc476.ge

Re: PowerPC prologue and epilogue 2

On Tue, Apr 17, 2012 at 11:12 AM, Alan Modra wrote: > This fixes a lot of confusion in rs6000_frame_related call arguments. > At the time rs6000_frame_related first appeared, the prologue only > used sp_reg_rtx (r1) or frame_ptr_rtx (r12) as frame_reg_rtx to access > register save slots.  If r12 w

Re: PowerPC prologue and epilogue 3

On Tue, Apr 17, 2012 at 11:13 AM, Alan Modra wrote: > This continues the prologue and epilogue cleanup.  Not many user > visible changes here, except for: > - a bugfix to the LR save RTL emitted by rs6000_emit_savres_rtx which >  may affect SPE, > - a bugfix for SPE code emitted when using a stati

Re: PowerPC prologue and epilogue 4

On Tue, Apr 17, 2012 at 11:13 AM, Alan Modra wrote: > This provides some protection against misuse of r0, r11 and r12.  I > found it useful when enabling out-of-line saves for large frames.  ;-) > >        * config/rs6000/rs6000.c (START_USE, END_USE, NOT_INUSE): Define. >        (rs6000_emit_prol

Re: PowerPC prologue and epilogue 5

On Thu, Apr 19, 2012 at 11:36 AM, Alan Modra wrote: > On Thu, Apr 19, 2012 at 08:00:15PM +0930, Alan Modra wrote: >> On Wed, Apr 18, 2012 at 12:45:16AM +0930, Alan Modra wrote: >> > This enables out-of-line save and restore for large frames, and for >> > ABI_AIX when using the static chain. >> >>

Re: [PATCH, powerpc] Fix PR47197

2012-04-24 Bill Schmidt PR target/47197 * config/rs6000/rs6000-c.c (fully_fold_convert): New function. (altivec_build_resolved_builtin): Call fully_fold_convert. 2012-04-24 Bill Schmidt PR target/47197 * g

Re: PowerPC prologue and epilogue 6

On Sat, Apr 21, 2012 at 2:48 AM, Alan Modra wrote: > This patch adds out-of-line vector saves and restores.  To do this I > made some infrastructure changes to various functions like > rs6000_emit_savres_rtx that currently take boolean parameters (savep, > gpr, and lr).  Rather than add yet anothe

Re: PowerPC prologue and epilogue 6

On Wed, Apr 25, 2012 at 1:20 AM, Alan Modra wrote: > This patch adds a testcase to verify register saves and restores. > I tried to write it so that it will run on all powerpc targets.  From > past experience it probably won't.  OK to apply anyway, and fix > fallout later? > >        * gcc.target

Re: [patch] backport powerpc64-freebsd support to 4.7 branch

On Sat, Apr 28, 2012 at 3:45 PM, Andreas Tobler wrote: > Hello all, > > I did a backport of the powerpc64-freebsd support to the 4.7 branch, here > the results: > > http://gcc.gnu.org/ml/gcc-testresults/2012-04/msg02768.html > http://gcc.gnu.org/ml/gcc-testresults/2012-04/msg02767.html > > Is the

Re: [RS6000] Fix PR53038, cfa_restore out of order

On Thu, Apr 26, 2012 at 1:00 AM, Alan Modra wrote: >        PR target/53038 >        * config/rs6000/rs6000.c (load_lr_save, restore_saved_lr, >        load_cr_save, add_crlr_cfa_restore): New functions. >        (rs6000_restore_saved_cr): Rename to.. >        (restore_saved_cr): ..this.  Add cfa

Re: fix ppc-aix build failures with spaces in CC (internal) variable

On Thu, May 3, 2012 at 6:19 AM, Olivier Hainque wrote: >> We sometimes get to invoke Makefile targets with a CC variable value >> containing >> spaces (for extra options, typically). This causes failure at some stages on >> powerpc-aix from mh-ppc-aix which has >> >>  LDFLAGS = `case $(CC) in *g

Re: [PATCH, powerpc] PR 53199, fix usage of __builtin_bswap64 on power6

On Thu, May 3, 2012 at 1:56 PM, Michael Meissner wrote: > In trying to build machine specific versions of glibc with newer compilers, we > ran into a bug where the current glibc would not build on power6.  This was > due > to glibc using the __builtin_swap64 builtin.  Power6 sets the > -mavoid-in

Re: fix mem+32760 ICE on powerpc - provide/use predicates weaker than mode_dependent_address_p

This is achieved by the introduction of a TARGET_MAY_NARROW_ACCESS target hook, which defaults to !mode_dependent_address_p and is redefined for powerpc. The patch uses this hook directly instead of the former predicate in a couple of places where this was the intent already, as well as new "valid_

Re: remove TARGET_E500 and factorize SPE defaults computation in powerpc ports

On Mon, May 7, 2012 at 12:10 PM, Joseph S. Myers wrote: > On Mon, 7 May 2012, Olivier Hainque wrote: > >> Joseph and David suggested to address this in a more general fashion, >> along lines proposed in >> >>   http://gcc.gnu.org/ml/gcc-patches/2010-08/msg01667.html >> >> The attached patch is a f

Re: remove TARGET_E500 and factorize SPE defaults computation in powerpc ports

On Mon, May 7, 2012 at 1:24 PM, Olivier Hainque wrote: > > On May 7, 2012, at 18:59 , David Edelsohn wrote: >> Yes, exactly.  If we can work through the fallout, this is exactly the >> type of cleanup I envisioned. > >  Great :) > >> Thanks, David > >  Do yo

Re: [RS6000] Fix PR53271 powerpc ports

On Tue, May 8, 2012 at 6:32 AM, Alan Modra wrote: > OK, the assert is doing its job.  I wanted to minimize the number of > places that need temporary hard regs, so that tracking of which hard > reg is in use can all be done in rs6000_emit_prologue. > > The problem is that the insns here need reg+

[PATCH] gcc_update explicit use of "svn"

contrib/gcc_update currently uses "svn" explicitly to determine the Revision and Branch instead of the $GCC_SVN shell variable used in other instances in the script. This patch uses the shell variable in all instances. Thanks, David * gcc_update: Use $GCC_SVN to retrieve branch and revisi

Re: Symbol table 19/many: cleanup varpool/front-end/varasm interactions

Jan, This patch is causing a bootstrap failure on AIX. It generates linker errors that TOC symbols are not emitted: ld: 0711-317 ERROR: Undefined symbol: LC..0 ld: 0711-317 ERROR: Undefined symbol: LC..1 ld: 0711-317 ERROR: Undefined symbol: LC..2 ld: 0711-317 ERROR: Undefined symbol: LC..3 ld:

Re: unwinding fallbacks for powerpc32 on aix 5.2 and 5.3

libgcc/ * config/rs6000/aix-unwind.h (ucontext_for): Helper for ... (ppc_aix_fallback_frame_state): New, implementation of ... (MD_FALLBACK_FRAME_STATE_FOR): Define. Please do not create another definition of the register number for LR. Earlier in the file it is defined as

Re: unwinding fallbacks for powerpc32 on aix 5.2 and 5.3

> libgcc/ >        * config/rs6000/aix-unwind.h (ucontext_for): Helper for ... >        (ppc_aix_fallback_frame_state): New, implementation of ... >        (MD_FALLBACK_FRAME_STATE_FOR): Define. I forgot to ask, is there a non-Ada, target-specific testcase that you can add to ensure this functiona

Re: unwinding fallbacks for powerpc32 on aix 5.2 and 5.3

On Mon, May 14, 2012 at 6:03 AM, Olivier Hainque wrote: > > On May 13, 2012, at 00:03 , David Edelsohn wrote: >> >> I forgot to ask, is there a non-Ada, target-specific testcase that you >> can add to ensure this functionality does not get broken? >> >> Thanks,

Re: unwinding fallbacks for powerpc32 on aix 5.2 and 5.3

On Mon, May 14, 2012 at 9:39 AM, Olivier Hainque wrote: > > On May 14, 2012, at 15:14 , David Edelsohn wrote: >> Yes, something like that test. >> >> Should the test go in g++.dg/eh or in g++.target/powerpc? > >  It's really about the general capability to h

Re: remove TARGET_E500 and factorize SPE defaults computation in powerpc ports

On Tue, May 15, 2012 at 9:47 AM, Olivier Hainque wrote: >        config/rs6000: > >        * rs6000-opts.h (enum processor_type): Add PROCESSOR_PPC8548. >        * rs6000-cpus.def: Reference it for cpu="8548". >        * rs6000.md (cpu attribute definition): Add ppc8548. >        * 8540.md: indic

Re: rs6000 toc reference rtl again

On Tue, May 1, 2012 at 12:17 AM, Alan Modra wrote: >        * config/rs6000/predicates.md (input_operand): Don't match >        constant pool addresses.  Remove label_ref, high and plus from >        match_code list.  Remove redundant CONSTANT_P test. >        (splat_input_operand): Similarly upd

Re: [PATCH, rs6000] Fix PR53385

On Fri, May 18, 2012 at 11:00 AM, William J. Schmidt wrote: > This repairs the bootstrap issue due to unsafe signed overflow > assumptions.  Bootstrapped and tested on powerpc64-unknown-linux-gnu > with no new regressions.  Ok for trunk? > > Thanks, > Bill > > > 2012-05-18  Bill Schmidt   > >    

Re: rs6000.c forward declaration cleanup

On Sun, May 20, 2012 at 9:57 PM, Alan Modra wrote: > This removes rather a lot of forward declarations in rs6000.c, most of > which existed to satisfy an early TARGET_INITIALIZER.  Now that the > TARGET_INITIALIZER has been moved to the end of rs6000.c, they become > unnecessary and wrongly give t

Re: [RS6000] save/restore reg tidy

On Sun, May 20, 2012 at 10:48 PM, Alan Modra wrote: > On Tue, May 08, 2012 at 08:02:39PM +0930, Alan Modra wrote: >> I also make use of gen_frame_store and siblings that I invented for >> generating the eh info, elsewhere in rs6000.c where doing so is >> blindingly obvious.  We could probably use

Re: [RS6000] out-of-line save/restore conditions

On Mon, May 21, 2012 at 1:14 AM, Alan Modra wrote: > Currently, powerpc-linux gcc -Os -mno-multiple uses out-of-line gpr > save and restore functions when saving/restoring just one gpr.  That's > quite silly since the function call requires more instructions and is > slower than an inline save/res

Re: [RFA] PowerPC e5500 and e6500 cores support

> Regarding the implementation of popcntb, popcntd, and cmpb. Gcc has > dedicated masks on target_flags for them, but due to shortage of bits, > those masks controls more than the name implies. The target flag bits control more than the name implies, but the bits correspond to published ISA levels

[PATCH] rs6000.c missing target hook

During one of the target hook conversions, rs6000_aix_asm_output_dwarf_table_ref() retained a use of TARGET_STRIP_NAME_ENCODING macro instead of the target hook, which broke when Alan cleaned up rs6000.c. Fixed thusly. - David * config/rs6000/rs6000.c (rs6000_aix_asm_output_dwarf_table_ref): Use

Re: [PATCH] rs6000.c missing target hook

On Tue, May 22, 2012 at 1:31 PM, Mike Stump wrote: >>   fprintf (asm_out_file, "\t.ref %s\n", >> -          TARGET_STRIP_NAME_ENCODING (frame_table_label)); >> +          (* targetm.strip_name_encoding) (frame_table_label)); > > Any reason to not remove (* and )? I wanted to be consistent with t

Re: [RFA] PowerPC e5500 and e6500 cores support

On Wed, May 23, 2012 at 10:18 AM, Edmar wrote: > David, Michael, > > Thanks for the feedback. > If you don't object, I will relay the message to the designers. > > Meanwhile I have to work with the cards I have, so... > I will break the patch in three parts: > - One that includes the very basic, s

Re: [PATCH, rs6000] Fix insertion of nop[s] to force dependent load into new dispatch group.

On Wed, May 23, 2012 at 11:48 AM, Pat Haugen wrote: > The following patch fixes existing code that tried to prevent load-hit-store > (LHS) from being in the same dispatch group. The main problem was use of the > wrong dependency list in is_costly_group(), but I also added code to verify > the memo

Re: [PATCH] Add powerpc64-linux configuration options

On Wed, May 23, 2012 at 6:36 PM, Michael Meissner wrote: > On powerpc64-linux systems that run on IBM servers, the 32-bit software > emulation library is not built with the Red Hat and SUSE distributions, but > the > FSF sources still list it as a multilib.  This patch adds a configuration > opti

Re: use longcall to abort from !pic trampoline setup on ppc-vxworks

libgcc/ * config/rs6000/vxworks/tramp.S (trampoline_setup): Use a longcall sequence in the non pic case on VxWorks. + addis 11, 0,JUMP_TARGET(abort)@ha Why do you use the addis mnemonic instead of lis mnemonic? Yes, lis X,Y is an alias for addis X,0,Y, but the simp

Re: [PATCH] Add powerpc64-linux configuration options

On Fri, May 25, 2012 at 10:22 AM, Michael Meissner wrote: > Yes, the second patch just does not build the library or use the > -mstrict-align > option.  It is much simpler, but there may be somebody out there that depends > on the functionality.  I really don't know, one way or the other. Mike,

Re: [PATCH] [PowerPC] [RFA] Fix PR target/53559 ICE on altivec builtins stv[l|r]x[l]

On Mon, Jun 4, 2012 at 10:08 AM, Edmar wrote: > I regression tested the patch presented in the PR: > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53559 > > for the following branches: > 4.5 branch svn revision 188125 > 4.6 branch svn revision 188124 > 4.7 branch svn revision 188128 > 4.8 trunk sv

Re: [PATCH] PR 53487 - Fix isel on powerpc to work again

On Mon, Jun 4, 2012 at 5:51 PM, Michael Meissner wrote: > This patch fixes PR 53487, so that -misel will no longer cause an unknown insn > error.  Andrew Pinksi's changes on May 4th, 2012, changed to use the > movcc pattern instead of the cstore4 in some cases, when a target > machine defines both

Re: [RFA] PowerPC e5500 and e6500 cores support

On Fri, Jun 1, 2012 at 11:57 AM, Edmar wrote: > Freescale would like to contribute these patches to gcc. > > It enables gcc for the new Freescale 64 bit cores. It creates a pipeline > description, and set proper default flags for the e5500 and e6500 cores. > > Some Altivec extensions for e6500 wil

Re: [RFC] [PowerPC] Patch to create new attribute type: popcnt

On Tue, Jun 5, 2012 at 4:21 PM, Edmar wrote: > David, Michael, > > Here is the new type "popcnt" patch that I had separated from previous > E5500/E6500 submission, also added the changes suggested by Michael > Meissner (detailed bellow). > I am missing some details for power6. (Could not find any

Re: [RFA] PowerPC e5500 and e6500 cores support

On Tue, Jun 5, 2012 at 3:13 PM, Edmar wrote: > The patch I submitted had an omission. I failed to regenerate > rs6000-tables.opt > (Sorry, I misunderstood gcc_update --touch instructions) > OK to commit the update ? > > 2012-06-05  Edmar Wienskoski > >    * config/rs6000/rs6000-tables.opt: Regene

Re: [PATCH] Add vector cost model density heuristic

On Mon, Jun 11, 2012 at 7:40 AM, Richard Guenther wrote: > Hmm.  I don't like this patch or its general idea too much.  Instead > I'd like us to move more of the cost model detail to the target, giving > it a chance to look at the whole loop before deciding on a cost.  ISTR > posting the overall

Re: [PATCH] Add vector cost model density heuristic

On Mon, Jun 11, 2012 at 10:48 AM, Richard Guenther wrote: > On Mon, 11 Jun 2012, David Edelsohn wrote: > >> On Mon, Jun 11, 2012 at 7:40 AM, Richard Guenther wrote: >> >> > Hmm.  I don't like this patch or its general idea too much.  Instead >> > I'd

Re: [PATCH] Add vector cost model density heuristic

On Mon, Jun 11, 2012 at 10:55 AM, Richard Guenther wrote: > Well, they are at least magic numbers and heuristics that apply > generally and not only to the single issue in sphinx.  And in > fact how it works for sphinx _is_ magic. > >> Second, I suggest that you need to rephrase "I can make you"

Re: [PATCH 3/3] rs6000: Rewrite sync patterns for atomic; expand early.

On Sat, Jun 9, 2012 at 10:40 AM, Richard Henderson wrote: > Nope.  I do see the obvious mistake in the atomic_load pattern though: > The mode iterator should have been INT1 not INT. Did you want to commit the fix for the iterator? > ... and for extra credit we ought to implement DImode atomic l

Re: [PATCH 3/3] rs6000: Rewrite sync patterns for atomic; expand early.

On Tue, Jun 12, 2012 at 11:51 AM, Richard Henderson wrote: > On 2012-06-11 18:40, David Edelsohn wrote: >>> > Nope.  I do see the obvious mistake in the atomic_load pattern though: >>> > The mode iterator should have been INT1 not INT. >> Did you want t

Re: [PATCH 3/3] rs6000: Rewrite sync patterns for atomic; expand early.

On Tue, Jun 12, 2012 at 9:40 AM, Richard Henderson wrote: >> I like your suggestion, but the PowerPC developer community does not >> uniformly appreciate that behavior. > > Surely there's a difference between gratuitously using fp registers > and that being the *only* way to implement a particula

Re: [patch] Remove NO_IMPLICIT_EXTERN_C target macro

On Mon, Jun 18, 2012 at 7:12 AM, Joseph S. Myers wrote: > On Mon, 18 Jun 2012, Steven Bosscher wrote: > >> For targets that do not define NO_IMPLICIT_EXTERN_C, GCC assumes that >> included system headers are implicitly wrapped in 'extern "C" {...}'. >> I could not find where this target macro was

[PATCH] AIX pthread.h fixincludes

AIX 5.2 pthread.h uses the wrong number of braces for more of the PTHREAD initializers. This patch extends the earlier patch to fix the other broken macros. * inclhack.def (aix_mutex_initializer_1, aix_cond_initializer_1, aix_rwlock_initializer): New. * fixincl.x: Regenerat

Re: Fix e500 vector ICE with string constants

On Tue, Jun 19, 2012 at 5:56 PM, Joseph S. Myers wrote: > 2012-06-19  Joseph Myers   > >        * config/rs6000/spe.md (*mov_si_e500_subreg0): Rename to >        mov_si_e500_subreg0. >        (*mov_si_e500_subreg0_elf_low) >        (*mov_si_e500_subreg4_elf_low): New patterns. > > testsuite: > 20

Re: [Target maintainers]: Please update libjava/sysdep/*/locks.h with new atomic builtins

libjava barriers, it probably can be used as a generic implementation for targets that support the __atomic intrinsics. - David 2012-06-20 David Edelsohn Alan Modra * sysdep/powerpc/locks.h (compare_and_swap): Use GCC atomic intrinsics. (release_set): Same

Re: [Target maintainers]: Please update libjava/sysdep/*/locks.h with new atomic builtins

On Wed, Jun 20, 2012 at 9:35 AM, Alan Modra wrote: > On Wed, Jun 20, 2012 at 09:10:44AM -0400, David Edelsohn wrote: >>  inline static void >>  release_set (volatile obj_addr_t *addr, obj_addr_t new_val) >>  { >> -  __asm__ __volatile__ ("sync" :

Re: [RS6000] atomic tweaks

On Thu, Jun 21, 2012 at 6:55 AM, Alan Modra wrote: > A couple of small tweaks to PowerPc atomic operations.  The first > omits the "cmp; bc; isync" barrier on atomic_load with mem model > __ATOMIC_CONSUME.  PowerPC pointer loads don't need a barrier.  Ref > http://www.rdrop.com/users/paulmck/scala

Re: [RFC] [PowerPC] Patch to create new attribute type: popcnt

On Wed, Jun 6, 2012 at 12:19 PM, Edmar wrote: > On 06/06/2012 08:57 AM, David Edelsohn wrote: >> >> On Tue, Jun 5, 2012 at 4:21 PM, Edmar  wrote: >>> >>> David, Michael, >>> >>> Here is the new type "popcnt" patch that I had separ

Re: Allow use of ranges in copyright notices

On Sat, Jun 30, 2012 at 10:58 AM, Joseph S. Myers wrote: > I propose that GCC should allow the use of ranges of years (e.g. > 1987-2012) in copyright notices on source files. As described at > : > > * This requires a notice in REA

<    5   6   7   8   9   10   11   12   13   14   >