[PATCH] RISC-V: Remove the redundant expressions in the and3.

When generating the gen_and3 function based on the and3 template, it produces the expression emit_insn (gen_rtx_SET (operand0, gen_rtx_AND (, operand1, operand2)));, which is identical to the portion I removed in this patch. Therefore, the redundant portion can be deleted. Signed-off-by: Die Li

[PATCH] RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV

be deleted. 2. Change operands[4] from const0_rtx to operands[1] to maintain rtl consistency. Although when output assembly, only operands[4] CODE will affect the output result. Signed-off-by: Die Li gcc/ChangeLog: * config/riscv/thead.md (*th_cond_gpr_mov): Delete. --- gcc/config/risc

[PATCH] RISC-V: Optimize TARGET_XTHEADCONDMOV

ret Signed-off-by: Die Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move_onesided): Delete. (riscv_expand_conditional_move): Reuse the TARGET_SFB_ALU expand process for TARGET_XTHEADCONDMOV gcc/testsuite/ChangeLog: * gcc.target/riscv

[PATCH] [RISC-V] Fix riscv_expand_conditional_move.

: ConNmv_reg_reg_reg: sub a1,a0,a1 th.mveqza2,zero,a1 th.mvneza3,zero,a1 or a0,a2,a3 ret Co-Authored by: Fei Gao Signed-off-by: Die Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode checking